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A Simplified Surface Potential Based Current Model for Gate-All-Around Carbon Nanotube Field Effect Transistor (GAA-CNFET)

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dc.contributor.author Gupta, Navneet
dc.date.accessioned 2023-02-04T06:22:43Z
dc.date.available 2023-02-04T06:22:43Z
dc.date.issued 2021
dc.identifier.uri dspace.unimap.edu.my/bitstream/handle/123456789/71435/A%20Simplified%20Surface%20Potential%20Based%20Current%20Model.pdf?sequence=1&isAllowed=y
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/8956
dc.description.abstract This paper presents a simple surface-potential based drain current (Id) model for gate-all-around carbon nanotube field effect transistor (GAA-CNFET). The model captures a number of features which include ballistic transport, first subband minima, chirality and non-existence of fringing and screening effect due to its geometry. Further, the effect of chirality on subthreshold swing (SS), current on/off ratio (ION/OFF) and transconductance (gm) is studied by extracting these parameters from drain current variation. It is observed that there exists a trade-off between the parameters for different chiral vector CNTs. As chirality increases, transconductance and subthreshold slope increases while current on/off ratio reduces. To confirm the validity of proposed model, virtually fabricated GAA-CNFET device performance was simulated and compared with the calculated values. The variation is also compared with the experimental result of actually fabricated device. The close match between calculated, simulated and experimental results confirms the validity of the proposed model. en_US
dc.language.iso en en_US
dc.subject EEE en_US
dc.subject Carbon nanotube en_US
dc.subject Carbon nanotube field effect transistor (CNFET) en_US
dc.subject Chirality en_US
dc.subject Device modeling en_US
dc.title A Simplified Surface Potential Based Current Model for Gate-All-Around Carbon Nanotube Field Effect Transistor (GAA-CNFET) en_US
dc.type Article en_US


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