| dc.contributor.author |
Gupta, Navneet |
|
| dc.date.accessioned |
2023-02-06T08:28:35Z |
|
| dc.date.available |
2023-02-06T08:28:35Z |
|
| dc.date.issued |
2017 |
|
| dc.identifier.uri |
https://ijneam.unimap.edu.my/images/PDF/IJNEAM%20No.%202,%202017/Vol_10_No_2_2017_2_101-110.pdf |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/8978 |
|
| dc.description.abstract |
In this paper, we have presented the effect of the density-of-states (DOS) parameters on the
performance of n-channel top gated staggered nc-Si TFT. The analysis was performed using
ATLAS 2D TCAD simulator from SILVACO. The variation in DOS in nc-Si material and
thus on the TFT device performance occurred by altering the channel length and channel
quality is presented. The simulation results reveal that the increase in channel length and the
degradation in channel quality degrade the trans-conductance and drain current. By iterating
the order of parasitic resistance and the value of characteristic decay energy related to
material quality, the same trend is achieved for simulated and experimental results for nc-
Si TFT with W/L=200μm/50μm |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
IJNeaM |
en_US |
| dc.subject |
EEE |
en_US |
| dc.subject |
Nanocrystalline Silicon |
en_US |
| dc.subject |
Thin film transistor (TFT) |
en_US |
| dc.subject |
TCAD |
en_US |
| dc.subject |
ATLAS |
en_US |
| dc.subject |
Channel length |
en_US |
| dc.subject |
Density of states (DoS) |
en_US |
| dc.title |
Two dimensional simulation and analysis of density-of-states ( DOS ) in top-gated nanocrystalline silicon thin film transistor ( nc-Si TFT ) |
en_US |
| dc.type |
Article |
en_US |