dc.contributor.author |
Gupta, Navneet |
|
dc.date.accessioned |
2023-02-06T10:57:31Z |
|
dc.date.available |
2023-02-06T10:57:31Z |
|
dc.date.issued |
2008 |
|
dc.identifier.uri |
https://www.worldscientific.com/doi/abs/10.1142/S0217979208049406 |
|
dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9009 |
|
dc.description.abstract |
This work presents the study of the effect of trap states at the oxide-silicon interface in lightly doped polycrystalline silicon thin-film transistors with large grains. In this study, it is assumed that the oxide-silicon interface traps are evenly distributed throughout the interface region and single grain boundary is present in the channel of poly-Si TFT. It is shown that improved device characteristics can be obtained by reducing the gate oxide thickness. It is also observed that as gate oxide thickness decreases for a constant value of trap state density in the oxide-silicon interface, the gate voltage required for channel formation is lowered and leads to a decrease in threshold voltage of the device. Calculated and experimental results are also found to be well consistent with each other. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
World Scientific |
en_US |
dc.subject |
EEE |
en_US |
dc.subject |
Thin film transistor (TFT) |
en_US |
dc.subject |
Silicon |
en_US |
dc.subject |
Polycrystalline silicon |
en_US |
dc.subject |
Trap states |
en_US |
dc.subject |
Threshold voltage |
en_US |
dc.title |
Effect of trap states at the oxide-silicon interface in polycrystalline silicon thin-film transistors |
en_US |
dc.type |
Article |
en_US |