dc.contributor.author |
Gupta, Navneet |
|
dc.date.accessioned |
2023-02-06T11:06:42Z |
|
dc.date.available |
2023-02-06T11:06:42Z |
|
dc.date.issued |
2006 |
|
dc.identifier.uri |
https://www.worldscientific.com/doi/10.1142/S0217984906010986 |
|
dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9013 |
|
dc.description.abstract |
The grain boundary scattering effects on carrier transport were studied analytically by considering the grains and grain boundaries that act as the series resistance in the channel of a polycrystalline silicon (poly-Si) thin-film transistor (TFT). Effective carrier mobility (μ*) and drain current (ID) variations were analyzed using the model by changing the grain boundary width (DGB) in the channel as a function of the gate voltage, in the linear region of the poly-Si TFT characteristic at room temperature. μ* and ID were computed for DGB ranging from 1 nm to 10 nm. It was found that for different values of the gate voltage, μ* and ID increased with a decrease in grain boundary width (DGB). A remarkable improvement was observed in device characteristics as DGB was decreased below 2 nm. The predicted results using the present model are in a reasonably good agreement with experimental results, hence confirming the validity of the model. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
World Scientific |
en_US |
dc.subject |
EEE |
en_US |
dc.subject |
Polysilicon thin-film transistor |
en_US |
dc.subject |
Grain boundary |
en_US |
dc.subject |
Effective carrier mobility |
en_US |
dc.title |
Effects of grain boundary width on transfer characteristics of polysilicon thin-film transistor |
en_US |
dc.type |
Article |
en_US |