Analytical modeling of carrier transport through transverse and longitudinal grain boundaries in polysilicon thin-film transistors

Abstract

Carrier transport through transverse and longitudinal grain boundaries (GBs) in polysilicon thin film transistors (poly-Si TFTs) has been studied. The model considers an array of square grains in the channel of poly-Si TFT in which current flows along the longitudinal GBs and through the grains and the transverse GBs. The variation of field-effect mobility (HFE) and drain current (ID) is computed for different values of grain size. This study reveals that at low gate voltage the longitudinal GBs are seen to influence the field-effect mobility and drain current. As gate voltage increases, the effect of transverse GBs is found to account for experimental results. This is attributed to the fact that at low gate voltage, the carriers moving through longitudinal GBs have more opportunities to be trapped at the trapping sites and as gate voltage increases the carriers have sufficient energy to bypass the longitudinal GBs and obstructed by transverse GBs alone. This may be the reason that the calculated effects of longitudinal GBs do not appear in the experimental results at high gate voltage