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Hardware Accelerators for Iris Localization

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dc.contributor.author Gupta, Anu
dc.contributor.author Asati, Abhijit
dc.date.accessioned 2023-02-09T09:34:25Z
dc.date.available 2023-02-09T09:34:25Z
dc.date.issued 2017-09
dc.identifier.uri https://link.springer.com/article/10.1007/s11265-017-1282-2
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9110
dc.description.abstract This paper presents field programmable logic array (FPGA) based hardware accelerators for iris localization, which can be used to accelerate the iris localization task in reliable and affordable embedded iris recognition systems. This work uses edge-map generation and circular Hough transform (CHT) based algorithm to localize irises in the images captured under near infrared (NIR) illumination. The proposed hardware accelerators for iris localization are: 1) Edge-map generation hardware for pupillary boundary detection; 2) Edge-map generation hardware for limbic boundary detection; and 3) CHT hardware for pupillary and limbic boundary detection. These hardware accelerators have processing time of 390.46 μsec, 393.67 μsec and 3.46 msec (average) respectively for an image of 320 × 240 pixels and achieve the iris localization accuracy of 96.52%. The proposed CHT and median filter hardware implementations show better results than the previous work. en_US
dc.language.iso en en_US
dc.publisher Springer en_US
dc.subject EEE en_US
dc.subject Field programmable logic array (FPGA) en_US
dc.subject Circular Hough Transform (CHT) en_US
dc.title Hardware Accelerators for Iris Localization en_US
dc.type Article en_US


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