dc.contributor.author |
Gupta, Anu |
|
dc.date.accessioned |
2023-02-09T10:01:36Z |
|
dc.date.available |
2023-02-09T10:01:36Z |
|
dc.date.issued |
2015-04 |
|
dc.identifier.uri |
https://www.tandfonline.com/doi/full/10.1080/00207217.2015.1082199 |
|
dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9115 |
|
dc.description.abstract |
This paper proposes a hardware-efficient low-power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor technology. The proposed TALU architecture combines adder-subtractor and Ex-OR cell in one cell, thereby reducing the number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimised at transistor level with a new pass-transistor logic-based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
Taylor & Francis |
en_US |
dc.subject |
EEE |
en_US |
dc.subject |
C-CMOS |
en_US |
dc.subject |
Carbon nanotube (CNT) field effect transistor (CNTFET) |
en_US |
dc.subject |
Ternary logic |
en_US |
dc.subject |
Ternary ALU (TALU) |
en_US |
dc.subject |
Power-delay product (PDP) |
en_US |
dc.title |
Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology |
en_US |
dc.type |
Article |
en_US |