Power-aware Design of Logarithmic Prefix Adders in Sub-threshold Regime: A Comparative Analysis

Abstract

This paper involves the design and comparative analysis of Han-Carlson and Kogge-Stone adders in sub-threshold regime using three different hybrid logic families. The performance metrics considered for the analysis of the adders are: power, delay and PDP. Simulation studies are carried out for 8, 16, 32 and 64 bit input data width. The proposed circuits show an energy efficient agreement with Spectre simulations using BSIM3v3 and BSIM4 models for 90 nm CMOS technology at 0.4 V supply voltage. The adder implementation outperforms its counterparts exhibiting low power consumption and lesser propagation delay as compared to conventional adders operated in the sub-threshold region.