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Performance Evalution Of CNTFET-Based Sram Cell Design

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dc.contributor.author Gupta, Anu
dc.date.accessioned 2023-02-09T11:02:03Z
dc.date.available 2023-02-09T11:02:03Z
dc.date.issued 2012
dc.identifier.uri https://www.interscience.in/cgi/viewcontent.cgi?article=1098&context=ijeee
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9125
dc.description.abstract Carbon Nanotube Field-Effect Transistor (CNTFET) technology with their excellent current capabilities, ballistic transport operation and superior thermal conductivities has proved to be a very promising and superior alternative to the conventional CMOS technology. A detailed analysis and simulation based assessment of circuit performance of this technology is presented here. As figures of merit speed, power consumption and stability are considered to evaluate the performance parameters of CNTFET-Based SRAM Cells with different chiral vectors for the optimum performance. A novel performance metric, presented as “SPR,” is used to assess these figures of merit. This comprehensive metric includes a metric of low power delay product (PDP) for write operation and high stability in the operation of a memory cell. It is shown that an 8T SRAM cell provides 73% higher SPR than Dual-Chiral based 6T SRAM cell for CNT technology and 124% higher SPR than its CMOS counterpart, thus attaining superior performance. The CNTFET-based 8T SRAM cell demonstrates that it provides high stability, low delay and low power, which is better than CNTFET-based 6T SRAM cell as well as CMOS SRAM cell. en_US
dc.language.iso en en_US
dc.publisher Inter Science en_US
dc.subject EEE en_US
dc.subject Carbon nanotube field effect transistor (CNTFET) en_US
dc.subject CNT en_US
dc.subject SNM en_US
dc.subject SINM (static current noise margin) en_US
dc.subject SPR en_US
dc.subject SRAM en_US
dc.title Performance Evalution Of CNTFET-Based Sram Cell Design en_US
dc.type Article en_US


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