Abstract:
The Logical Effort model is mainly to reduce delay in
a circuit, but does not show how to minimize power and area. This
paper deals with an empirical modeling and design of logical
effort for estimating power in CMOS logic gates. The power is
estimated in a circuit using the power of standard inverter and the
relationship established between Power (P) and Logical Effort (g),
Electrical Effort (h) and Parasitic (p) have been proposed in this
paper. To verify the above model a full adder circuitry producing
just the carry-out in UMC 90nm CMOS technology having supply
voltage of 1V is selected. The results obtained from the model are
accurate to 85.5% of the values obtained. The tool used is cadence
and the simulation is performed using spectre.