| dc.contributor.author |
Gupta, Anu |
|
| dc.date.accessioned |
2023-02-10T03:57:53Z |
|
| dc.date.available |
2023-02-10T03:57:53Z |
|
| dc.date.issued |
2009 |
|
| dc.identifier.uri |
https://citeseerx.ist.psu.edu/document?repid=rep1&type=pdf&doi=e4053b042b25ed657dd7fb62aa7d8aae7b313cdc |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9130 |
|
| dc.description.abstract |
This paper proposes an approach for designing a
R-2R 10 bit Digital to Analog Converter (DAC) which could
be made to operate at low voltage supply by efficiently
exploiting the cascaded Operational Amplifier (Op-Amp)
architecture. The DAC operates at a 3V power supply with
a settling time of 50-100ns , dynamic range of around 50-60
dB for signals upto a frequency of 10Mhz. Graph &
simulation results are provided to verify the stability of the
Op-Amp used in DAC |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
ACEEE |
en_US |
| dc.subject |
EEE |
en_US |
| dc.subject |
Cascaded Op-Amp Topology |
en_US |
| dc.subject |
DAC |
en_US |
| dc.subject |
Digital to Analog Converter |
en_US |
| dc.title |
Design of 10-bit Digital to Analog Converter Using Cascaded Operational Amplifier Topology |
en_US |
| dc.type |
Article |
en_US |