| dc.contributor.author |
Gupta, Anu |
|
| dc.date.accessioned |
2023-02-10T04:30:38Z |
|
| dc.date.available |
2023-02-10T04:30:38Z |
|
| dc.date.issued |
2009 |
|
| dc.identifier.uri |
https://ieeexplore.ieee.org/document/5328051 |
|
| dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9136 |
|
| dc.description.abstract |
Working with low frequency universal charge recovery logic (CRL) based NAND gate, the leakage current results in gradual charge up of the output node resulting in an incorrect output. A better implementation of the same circuit which increases the output resistance for the leakage current is used to mitigate this drawback in this paper. Also an analysis of the effect of rise time of clock edge on power dissipation of the split charge recovery logic (SCRL) based NAND gates has also been done. |
en_US |
| dc.language.iso |
en |
en_US |
| dc.publisher |
IEEE |
en_US |
| dc.subject |
EEE |
en_US |
| dc.subject |
Leakage current |
en_US |
| dc.subject |
Circuits |
en_US |
| dc.subject |
Frequency |
en_US |
| dc.subject |
Rails |
en_US |
| dc.subject |
Logic |
en_US |
| dc.subject |
Power engineering and energy |
en_US |
| dc.title |
Improved Implementation of CRL and SCRL Gates for Ultra Low Power |
en_US |
| dc.type |
Article |
en_US |