| dc.contributor.author | Gupta, Anu | |
| dc.date.accessioned | 2023-02-10T04:33:44Z | |
| dc.date.available | 2023-02-10T04:33:44Z | |
| dc.date.issued | 2012 | |
| dc.identifier.uri | https://link.springer.com/chapter/10.1007/978-3-642-31494-0_1 | |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9137 | |
| dc.description.abstract | A new CMOS Analog Multiplier in Current Domain using very negligible amount of static power is presented. This circuit uses the concept of harmonics along with the square law of current in a saturated MOS and is simulated using 90nm Technology Node of UMC. The supply voltage Vdd is kept at +1V. The circuit, when drawn using the Cadence Virtuoso Schematic Editor and simulated using the Spectre Simulator, gave a -3dB bandwidth of 2.07GHz with a load capacitance of 10fF. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | Springer | en_US |
| dc.subject | EEE | en_US |
| dc.subject | Analog | en_US |
| dc.subject | Multiplier | en_US |
| dc.subject | Low power | en_US |
| dc.subject | Current mode | en_US |
| dc.subject | Static power consumption | en_US |
| dc.title | An Efficient High Frequency and Low Power Analog Multiplier in Current Domain | en_US |
| dc.type | Book chapter | en_US |
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