DSpace Repository

Frequency compensation in two-stage operational amplifiers for achieving high 3-dB bandwidth

Show simple item record

dc.contributor.author Gupta, Anu
dc.date.accessioned 2023-02-10T10:15:51Z
dc.date.available 2023-02-10T10:15:51Z
dc.date.issued 2013
dc.identifier.uri https://ieeexplore.ieee.org/document/6731187?reload=true
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9156
dc.description.abstract A frequency compensation technique for achieving high 3-dB bandwidth in two-stage operational amplifiers is demonstrated in this paper. Due to the phenomenon of pole splitting in Miller's Compensation technique in classical op-amp, the 3-dB bandwidth reduces drastically. The technique demonstrated in this paper is a modification of Miller's Compensation technique to achieve a significant improvement in the 3-dB bandwidth by introducing an extra stage, consisting of MOS transistors (MOST). The coupling capacitor and a PMOS transistor operating in triode region is connected between the output of the extra stage and the input of the second stage. The simulations were carried out in Cadence VIRTUOSO environment using 0.18 μm CMOS process technology. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject 3-dB Bandwidth en_US
dc.subject Phase Margin en_US
dc.subject Two-Stage Operational Amplifier en_US
dc.subject Coupling Capacitor en_US
dc.subject Frequency Compensation en_US
dc.title Frequency compensation in two-stage operational amplifiers for achieving high 3-dB bandwidth en_US
dc.type Article en_US


Files in this item

Files Size Format View

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record

Search DSpace


Advanced Search

Browse

My Account