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Novel design of ternary magnitude comparator using CNTFETs

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dc.contributor.author Gupta, Anu
dc.date.accessioned 2023-02-10T10:52:40Z
dc.date.available 2023-02-10T10:52:40Z
dc.date.issued 2014
dc.identifier.uri https://ieeexplore.ieee.org/document/7030447
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9159
dc.description.abstract This paper proposes a novel design of 1-bit ternary magnitude comparator (TMC) using carbon nano tube field effect transistors (CNTFETs). The proposed 1-bit TMC is designed for pass transistor logic style in order to achieve low transistor count. Further, proposed design is used in realization of n-bit TMC which utilizes static binary tree configuration to correct the voltage levels and minimizes the number of stages to get high performance. Synopsis Hspice simulation results demonstrate that the proposed TMC for 4-bit operand length is 15% faster or 14% energy efficient with 32% less number of transistors, in comparison with CNTFET-based designs, recently published in the literature. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Carbon nanotube (CNT) field effect transistor (CNTFET) en_US
dc.subject Ternary logic en_US
dc.subject Ternary magnitude comparator (TMC) en_US
dc.title Novel design of ternary magnitude comparator using CNTFETs en_US
dc.type Article en_US


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