Abstract:
Rapid increases in chip complexity, increasingly faster clocks and proliferation of portable devices have combined to make power dissipation an important design parameter. In battery operated digital devices the demand of low power consumption and low energy dissipation in order to maximise battery life are the matter-of-course. Typical energy optimisation measures include voltage scaling and operating at the slowest possible speed. In this paper, to satisfy the low power requirement, sub-threshold logic that involves scaling voltage below the device threshold is being used. The proposed implementation lays emphasis on the usage of hybrid logic with reverse body biasing schemes which reduces high power consumption while giving lesser propagation delay and lesser area in sub-threshold regime. This scheme has been demonstrated on 4-bit, 16-bit and 64-bit carry look-ahead adders and simulated using TSMC 180 nm CMOS technology at 0.4 V supply voltage. Post-layout simulations show significant improvement, exhibiting low power consumption and lesser propagation delay as compared to conventional carry look-ahead adder