dc.contributor.author | Gupta, Anu | |
dc.date.accessioned | 2023-02-11T04:10:50Z | |
dc.date.available | 2023-02-11T04:10:50Z | |
dc.date.issued | 2019 | |
dc.identifier.uri | https://ieeexplore.ieee.org/document/8702598 | |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9170 | |
dc.description.abstract | Differential Power analysis (DPA) method is frequently used for non-invasive side-channel attack to hack into the system. This paper proposes a novel DPA attack immune design of FinFET based logic gates which show dense distribution of autocorrelation with salience strength of 38.11%. The proposed design has highly regular structure with exactly similar evaluation path for both differential outputs, AND-NAND, and OR-NOR which can be easily extended for n-bit inputs. The design effort is minimal as proposed structure is such that AND-NAND design can be used to obtain OR-NOR function by just changing the placement of inputs. These gates take 40 ps to evaluate the logic and consume 4.69 μ W/cycle. The designs are simulated using Symica Custom IC Design toolkit with ASAP7-7nm FinFET Low Threshold Voltage (LVT) technology with power supply of 700 mV. | en_US |
dc.language.iso | en | en_US |
dc.publisher | IEEE | en_US |
dc.subject | EEE | en_US |
dc.subject | Hardware Security | en_US |
dc.subject | Digital Circuits | en_US |
dc.subject | Logic gates | en_US |
dc.subject | Cryptography | en_US |
dc.title | Differential Power Analysis Immune Design of FinFET Based Novel Differential Logic Gate | en_US |
dc.type | Article | en_US |
Files | Size | Format | View |
---|---|---|---|
There are no files associated with this item. |