dc.contributor.author |
Asati, Abhijit |
|
dc.contributor.author |
Shekhar, Chandra |
|
dc.date.accessioned |
2023-03-01T11:13:35Z |
|
dc.date.available |
2023-03-01T11:13:35Z |
|
dc.date.issued |
2020-07 |
|
dc.identifier.uri |
https://link.springer.com/article/10.1007/s12652-020-02403-2 |
|
dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9414 |
|
dc.description.abstract |
Connected smart vehicles in automotive industries have increased, resulting in high vehicle-to-vehicle, vehicle-to-infrastructure,
and vehicle-to-cloud connectivity. Increased data rates are required to achieve high bandwidth requirements to support
such communication networks. Despite having numerous advantages, high connectivity between devices poses threats to
vehicle and human security, rendering encryption critical before transmitting data across vehicular networks. Advanced
encryption standard (AES) is commonly used for data encryption in automotive microcontrollers. Owing to modern digital
design complexities, field-programmable gate arrays (FPGAs) are attracting attention for pre-silicon verification and
software development. Owing to their parallel architectures, FPGAs are ideal for prototyping automotive designs running
encryption algorithms, like AES at real-time data rates. Moreover, because they are reconfigurable, prototyping results of
different implementation choices can be verified at an early stage, thereby helping architects and designers with forthcoming
optimal designs. FPGAs also serve as platforms to develop software considerably before silicon arrives, thereby decreasing
the time to market. Herein, we propose a high-throughput FPGA implementation of the AES algorithm for automotive
microcontrollers using a 128-bit key created via Vivado high-level synthesis (HLS) tool. We use HLS design method based
on application-specific bit widths to implement the design on FPGA. The generated design is implemented and verified using
Xilinx Kintex 7 and Virtex 6 FPGA; despite identical resource utilization (Look up tables and Flip-Flops), the throughput
results are superior to those obtained previously |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
Springer |
en_US |
dc.subject |
EEE |
en_US |
dc.subject |
Advanced encryption standard (AES) |
en_US |
dc.subject |
Field-programable gate array (FPGA) |
en_US |
dc.subject |
Very large scale integration (VLSI) |
en_US |
dc.subject |
High-level synthesis (HLS) |
en_US |
dc.subject |
Vivado high-level synthesis · |
en_US |
dc.title |
RETRACTED ARTICLE: High-throughput field-programable gate array implementation of the advanced encryption standard algorithm for automotive security applications |
en_US |
dc.type |
Article |
en_US |