Abstract:
Barrel shifters are often required for performing
data shifting and rotation in many key computer operations
from address decoding to computer arithmetic. In this
paper we present a comparative study of various
parameters like delay, power and area, for a high
performance 16-bit barrel shifter VLSI implementations
using three different logic design styles (conventional
CMOS, transmission gate CMOS and Dual rail Domino
CMOS logic) in 0.6mm, N-well CMOS process. The
proposed barrel shifter implementations shows better
performance as compared to implementation by R. Pereira