dc.contributor.author | Asati, Abhijit | |
dc.date.accessioned | 2023-03-02T11:15:34Z | |
dc.date.available | 2023-03-02T11:15:34Z | |
dc.date.issued | 2021-05 | |
dc.identifier.uri | https://link.springer.com/chapter/10.1007/978-981-33-6981-8_27 | |
dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9443 | |
dc.description.abstract | Dynamic voltage and frequency scaling (DVFS) is useful for low power digital circuit design. The work proposes a novel DVFS module offering any finer clock frequency change to produce an appropriate supply voltage to feed a digital circuit driven by DVFS module. In DVFS with varying supply and clock conditions the chances of setup and hold timing violations in D flip-flop (DFF) circuit may increase. The DVFS module driving a digital circuit utilizing Razor D flip-flop is used to correct errors occurring due to timing violations. The proposed circuit simulation shows that DVFS module driving simple D flip -flop shows error due to timing violations, while the DVFS module driving Razor D flip-flop shows the correct operation. In the digital pipelined circuits any occurrence of timing violations, the Razor DFF uses the error correction mechanism to prevent data loss with a penalty of one additional clock cycle. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Springer | en_US |
dc.subject | EEE | en_US |
dc.subject | DVFS | en_US |
dc.subject | Static power | en_US |
dc.subject | Dynamic power | en_US |
dc.subject | Transmission gate (TG) | en_US |
dc.title | An Improved DVFS Circuit & Error Correction Technique | en_US |
dc.type | Article | en_US |
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