| dc.contributor.author | Asati, Abhijit | |
| dc.contributor.author | Shekhar, Chandra | |
| dc.date.accessioned | 2023-03-03T05:30:23Z | |
| dc.date.available | 2023-03-03T05:30:23Z | |
| dc.date.issued | 2009 | |
| dc.identifier.uri | https://ieeexplore.ieee.org/abstract/document/5395495 | |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9459 | |
| dc.description.abstract | The PMOS/NMOS width ratio (ß) and W/L ratio of NMOS device is an important ratio in the design of digital logic cells using conventional CMOS logic design style. In this paper we propose a simulation-based method applied to CMOS inverter to accurately estimate an optimum W/L ratio of NMOS device and PMOS/NMOS width ratio when fanout loading of 1, 4 and 8 cells of similar type are present. The appropriate selection of W/L ratio of NMOS device and PMOS/NMOS width ratio makes the digital design faster and reduces the power consumption. | en_US |
| dc.language.iso | en | en_US |
| dc.publisher | IEEE | en_US |
| dc.subject | EEE | en_US |
| dc.subject | Inverters | en_US |
| dc.subject | MOS devices | en_US |
| dc.subject | CMOS logic circuits | en_US |
| dc.subject | Logic design | en_US |
| dc.subject | Logic devices | en_US |
| dc.subject | Logic gates | en_US |
| dc.subject | Circuit noise | en_US |
| dc.subject | CMOS technology | en_US |
| dc.title | Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load | en_US |
| dc.type | Article | en_US |
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