dc.contributor.author |
Chaturvedi, Nitin |
|
dc.date.accessioned |
2023-03-14T11:11:15Z |
|
dc.date.available |
2023-03-14T11:11:15Z |
|
dc.date.issued |
2013-07 |
|
dc.identifier.uri |
10.5121/ijdps.2013.4404 |
|
dc.identifier.uri |
http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9724 |
|
dc.description.abstract |
Advances in Integrated Circuit processing allow for more microprocessor design options. As Chip
Multiprocessor system (CMP) become the predominant topology for leading microprocessors, critical
components of the system are now integrated on a single chip. This enables sharing of computation
resources that was not previously possible. In addition the virtualization of these computation resources
exposes the system to a mix of diverse and competing workloads. On chip Cache memory is a resource of
primary concern as it can be dominant in controlling overall throughput. This Paper presents analysis of
various parameters affecting the performance of Multi-core Architectures like varying the number of
cores, changes L2 cache size, further we have varied directory size from 64 to 2048 entries on a 4 node, 8
node 16 node and 64 node Chip multiprocessor which in turn presents an open area of research on multicore
processors with private/shared last level cache as the future trend seems to be towards tiled
architecture executing multiple parallel applications with optimized silicon area utilization and excellent
performance. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
IJDPS |
en_US |
dc.subject |
EEE |
en_US |
dc.subject |
Chip Multiprocessors (CMP) |
en_US |
dc.subject |
Multiple-Chip Multiprocessor (M-CMP) |
en_US |
dc.subject |
Tiled Architecture |
en_US |
dc.title |
Study of Various Factors Affecting Performance of Multi-Core Processors |
en_US |
dc.type |
Article |
en_US |