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A Novel Decoder Design for Logic Computation in SRAM: CiM-SRAM

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dc.contributor.author Chaturvedi, Nitin
dc.date.accessioned 2023-03-15T05:31:39Z
dc.date.available 2023-03-15T05:31:39Z
dc.date.issued 2021
dc.identifier.uri https://ieeexplore.ieee.org/document/9691664
dc.identifier.uri http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9727
dc.description.abstract Computing-in-Memory is an emerging paradigm that promises to accelerate data-intensive computation by eliminating the back and forth data movement between the memory and processor. SRAM is an ideal candidate for implementing computation in memory as it offers benefits such as high speed, low power consumption, and high endurance. One of the most extensively explored techniques utilized to realize computation within the SRAM is reading out the voltage at the bitline, which corresponds to a valid logic function output. It also requires activation of multiple wordlines corresponding to the location of the stored operands in the memory. However, conventional address decoders in SRAM selects only one address at a time. Hence, addressing this challenge, we propose to design a novel decoder which support enabling of multiple wordline in a 6T bitcell based CiM-SRAM (Computing-in-Memory based SRAM) array for performing logic computation. en_US
dc.language.iso en en_US
dc.publisher IEEE en_US
dc.subject EEE en_US
dc.subject Address Decoders en_US
dc.subject Computing-in-Memory en_US
dc.subject Static Random-Access Memory en_US
dc.subject 6T bitcell en_US
dc.subject Peripheral circuits en_US
dc.title A Novel Decoder Design for Logic Computation in SRAM: CiM-SRAM en_US
dc.type Article en_US


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