Abstract:
Using FinFET for designing of SRAM cells has shown a great deal of advantages over planar bulk devices due to the additional control on the gates and due to fully depleted behavior. The improvements have been noted in sub-threshold slope, drive currents, short-channel effects and mismatches. As the memories become denser, the stability of the SRAM cells becomes a point of great concern. This calls for the need of assist circuitry for improving the reliability and stability of the cells. In this work, a write assist technique is discussed to improve the stability of the device. This design decreases the WL CRIT drastically and reduces the write delay of the cell. The simulations have been carried out on HSPICE with 32 nm PTM libraries for FinFET.