| dc.description.abstract |
Although the power density is said to be constant according to Dennard Scaling Model, the energy efficiency has not scaled along in the last decade. With increase in integration of transistors, the power budget is no longer balanced while moving from one technology node to another. Because of this the power density is no longer constant and it is now increasing with technology scaling. In successive generations the percentage of chip that can be switched at full frequency is dropping exponentially. This problem of Dark Silicon [1] is forcing the designers to power on only a few on-chip resources [2] at a time in order to avoid hitting the maximum power utilization mark. If we keep neglecting the Power density issue it is said that the microprocessors will soon have power density comparable to that of the sun at around 10,000W/cm2. Heterogeneous computing [3] is one of the proposed solutions to effectively tackle the power problem with increasing number of transistors. It has been crucial in increasing the performance and energy efficiency. A Heterogeneous Architecture has the potential to match each application to the best suited core. In Heterogeneous Architectures, each application can be matched to the best suited core in order to efficiently run the application. This solves the problem where most applications under utilize the hardware and there is very little performance drop when the same application is run on a less powerful processor. Dark Silicon also opens up new possibilities for integrating Hardware Accelerators which can be scheduled dynamically or statically. In Heterogeneous systems, the large number of exchanges between cores also contribute to the increase in power consumption. The interconnects also play an important role in energy efficiency. This paper focuses on identifying and highlighting some of the critical challenges faced due to Dark Silicon. The paper also lists down some initial research efforts to tackle these issues. |
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