Browsing by Author "Mishra, Neeraj"

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ABB Assisted Area Efficient Vernier Delay Line Time-to-Digital Converter for Low Voltage Applications
(IEEE, 2023-11) Mishra, Neeraj
We propose an Adaptive Body Biasing (ABB) assisted method for the improvement in resolution and reduction in on-chip area of time-to-digital converter (TDC). The proposed method also improves the metastability window with reduced hold time while maintaining the setup time same as conventional architecture of True Single-Phase Clock (TSPC) D flip flops (DFFs). In this article, we use Positive Edge Triggered (PET) TSPC DFFs for our analysis, which exhibit a significant hold time but benefit from a zero-setup time. Further, with the application of ABB, the desired delay difference between the delay lines of Vernier TDCs is achieved without having any area overhead. The simulation work is carried out using a 28 nm Fully Depleted Silicon-On-Insulator (FDSOI) technology node of STMicroelectronics (STM) at a voltage supply (V DD ) of 0.6 V.
Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort
(IEEE, 2022-12) Mishra, Neeraj
A static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ( t ). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t . A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.
Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure
(IEEE, 2023-07) Mishra, Neeraj
This article proposes a method for performing device-level variability-aware static timing analysis (STA) on digital circuits using a tool flow methodology based on Python and Bash scripting. The method involves creating an effective current source model (ECSM) .libs file with a custom tool flow, which incorporates variation-aware timing models of standard cells to minimize recharacterization efforts. The resulting file is integrated into an industry-standard STA tool environment to assess the impact of device and layout level variability on digital timing closure. The simulation work is carried out using Mentor Graphics ELDO SPICE, Synopsys DC Compiler, and PrimeTime STA environment in STMicroelectronics (STM) 65 nm CMOS process. This tool flow reduces recharacterization efforts by 98.13% compared to conventional SPICE simulation by incorporating the impact of device-level variability on the conventional STA flow.
DAAS: differential aging-aware STA for precise timing closure with reduced design margin
(IEEE, 2025-08) Mishra, Neeraj
This article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage (Vth) denoted by (Vth) in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of (Vth) is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28 nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately 99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.
Delay Modulation in Separately Driven Delay Cells Utilized for the Generation of High-Performance Multiphase Signals Using ROs
(IEEE, 2021-05) Mishra, Neeraj
This brief presents a general technique for achieving the highest possible RO oscillation frequency accompanied by lower phase noise in an enhanced circuit design utilizing novel delay cells. The circuit architecture has the delay cells’ inputs separated by an optimized skew offset. Skew-offset optimization is attained by integrating a pre-charge/discharge auxiliary feed-forward loop into the separately driven delay cells. This technique reduces the transition time when Supply and GND are simultaneously connected/disconnected to the delay cell’s output node. When these delay cells are connected in loops to form a Ring Oscillator, they provide high performance, even/odd multi-phase signals. The proposed methodology is validated in commercial 65nm and 180nm CMOS technologies. The post-layout simulations show that the proposed designs improve the performance by modulating the delay cell output node’s charging and discharging. The operating frequency of the proposed design, e.g., for odd stage 5/7 and even stage 4/8/16 stage, is almost 50%/40%, (80%/30%/20%) higher than that of the MSSRO (Multi-Loop Skew based Single-ended Ring Oscillator) with the same number of stages. Additionally, the designs proposed for the targeted phase noise and center frequency consume around 8–20% (odd stages)/ (6–28%) (Even stages) lesser power, a lower supply sensitivity up to 9%, and lower PVT variability up to 6% compared to its equivalent stages MSSRO (3-stages single-ended RO) counterparts in 180 nm CMOS Technology.
Design and Characterization of Bulk Driven MOS Varactor based VCO at Near Threshold Regime
(IEEE, 2018-10) Mishra, Neeraj
A wide tuning range, low VCO gain and a low PVT variations are the requirements for Ring Oscillators at near threshold voltages (NTV). Current starved ring oscillators (CSRO) have voltage headroom issues in NTV regime. A MOS varactor based single ended ring oscillator (SERO) is best suited for its full swing characteristics, wide tuning range and low power consumption. However, a high VCO gain and nonlinearity are its limitations. This paper proposes a bulk driven MOS varactor based SERO (BD-MOS) that gives low VCO gain and a linear tuning from 0 to VDD in NTV regime. Post layout simulations have been performed on parasitic extracted netlist using HSPICE in industrial 65nm CMOS process design kit (PDK). The design is based on an analysis of MOS varactor capacitance done using 2D-Synopsis TCAD mixed-mode simulations.
Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals
(IEEE, 2019-12) Mishra, Neeraj
This brief presents a general approach for generating high-frequency multiphase signals (even/odd), low phase noise, low power, and reduced supply sensitivity ring oscillators (ROs). For the same, multi-loop skew based single-ended ring oscillators (MSSROs) are designed and systematic analysis is performed. The topology is based on a unique feedback/feed-forward mechanism for realizing a fast loop in a long chain RO wherein the PMOS/NMOS of the stages are separately driven. This unique connection in MSSROs results in a skew offset (negative/positive/zero) which is generated between the inputs of PMOS/NMOS as the number of stages are increased. Therefore, MSSROs provide the time period equal to that of 3-stage single-ended conventional ROs (SCRO) and a better phase noise (7–11%) even with a larger number of stages (even/odd). A model is developed to predict the oscillation frequency and skew offset. The proposed methodology is validated in commercial 65nm and 180nm CMOS technologies, also indicating scalability of the proposed designs at scaled CMOS nodes. The simulations show that, depending on the number of stages, the operating frequency of the MSSROs varies from −25 (−11) % (positive-skew) to +16 (13) % (negative-skew) of its 3-stage SCRO counterparts in the 180nm (65nm) CMOS technology. Moreover, for a target phase noise and center frequency, the MSSROs consume about 8–30 (5–23) % lower power and up to 8% lower supply sensitivity as compared to its 3-stage SCRO counterparts in the 180nm (65nm) CMOS technology. The MSSRO also has a better PVT variation tolerance compared to SCRO.
An Efficient and Accurate Variation-Aware Design Methodology for Near-Threshold MOS-Varactor-Based VCO Architectures
(IEEE, 2020-11) Mishra, Neeraj
In this article, a variation-aware design methodology for high-performance MOS-varactor voltage-controlled ring oscillator (MV-VCRO) in near-threshold-voltage (NTV) regime is proposed. The MV-VCRO is suitable because it eliminates series-stack transistors and generates rail-to-rail swing. For the first time, delay-models for conventional, bulk-driven (BD), and dynamic-threshold (DT) MV-VCROs considering nonlinearity in NTV regime is presented using effective drive current ( I eff ) and MOS-varactor capacitance models. The proposed design methodology is intuitive and considers process-voltage-temperature (PVT) variations at an initial stage of the design for width-length optimization. The methodology is highly efficient and does not require performing time-consuming Monte-Carlo (MC) simulations at post-layout stages. Look-up tables (LUTs) for MOS-varactor average-capacitances, and I eff are generated while considering the regions of device operation during MV-VCRO output-node transitions while extracting the model parameters from one-time simulations. This approach is physics/topology-based and is verified in HSPICE and Sentaurus 2-D-TCAD simulations using STM65nm and 32 nm, respectively. The I eff -models predict the oscillation frequency ( f OSC ) with an accuracy of 97%, 96%, 97% for conventional, BD, DT-MV-VCRO, respectively. Furthermore, our estimated LUT- I eff -capacitance models account for the change in f OSC , tuning range, and voltage-controlled oscillator (VCO)-gain with PVT variations with an accuracy-efficiency of 96%-99% compared to MC simulations. Furthermore, using LUTs, phase-noise, power consumption, and layout-area optimization technique is presented for a particular f OSC . Finally, the design methodology ensures that the desired f OSC is within the “linear” range of the VCO's-gain due to statistical variation of V th , V DD , etc. This ensures resilience to PVT variations for NTV-VCO in linear feedback systems.
Generalized Edge Propagation and Multi-Band Frequency Switching Mechanism for MSSROs
(IEEE, 2023-04) Mishra, Neeraj
In this brief, generalized Phase Sequence and multi-band Frequency Switching mechanisms in Multi-Loop Separately-Driven Skew-Based Ring Oscillators (MSSROs) are presented for the first time. Compared to inverter-based Conventional Ring Oscillators (CROs), MSSROs can generate high-frequency multi-phase outputs with lower noise for a fixed power budget. However, delay cell connection schemes and resulting phase sequences for achieving lower frequencies have never been explored in MSSROs, limiting their use in sampling applications. This brief provides a detailed design methodology for producing multi-phase MSSRO outputs in a wide frequency range at pre-defined sequences. These guidelines are validated with post-layout simulations in 180/65nm CMOS for MSSROs oscillating at frequencies equivalent to 3, 5, 7, and 9-stage CROs. Finally, comparisons for frequency, FoM, and PVT sensitivity between the proposed topologies and CROs pose their usefulness as a viable clocking alternative.
Influences of Source/Drain Extension Region on Thermal Behavior of Stacked Nanosheet FET
(IEEE, 2024-01) Mishra, Neeraj
A well-calibrated numerical-simulation-based study reveals that an elongated extension region can be a notable approach for the self-heating mitigation of nanosheet FETs. It is observed that a longer extension length ( LEXT = 8 nm) reduces the ON current; however, it holds a smaller penalty in ION degradation (~10%) due to the self-heating effect (SHE). When the extension region is increased from 2 to 8 nm, a reduction of 16× in IOFF is observed along with a reduction of ~9 mV/dec in the subthreshold swing. On the contrary, a change in ~15 mV in VT is observed when LEXT is increased from 2 to 8 nm. Considering lattice heat due to SHE, intrinsic delay, unity-gain bandwidth, and the above-mentioned characteristic, the optimum LEXT would be 5–6 nm. The longer extension lengths (2–8-nm increase) provide a lesser transconductance ( gm ) degradation (~15%) due to SHE. It is observed that intrinsic capacitance Cgg reduces with an increment in LEXT (2–8 nm), which eventually reduces the propagation delay (~20%) with an improvement in noise margin too. It is worth noting that for a common source amplifier, a longer extension region of 8 nm will also provide ∼1.87× more voltage gain when compared with LEXT of 2 nm, which increases to ∼1.97× in self-heating condition due to a smaller degradation “ ΔG ” (from ~12.4% to ~6.6%) in gain with longer extension length
MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing Techniques
(IEEE, 2019-05) Mishra, Neeraj
Due to small output swings and series stack transistors, Differential Ring Oscillators (DRO) and current starved ROs are not well suited for Near Threshold Voltage (NTV) regime. MOS varactor based Single Ended Ring Oscillators (SERO) is well suited in NTV regime as it gives full swing characteristics, wide tuning range and has very low power consumption. This paper proposes different architectures using MOS Varactor SERO (VBRO) that gives high oscillation frequency, wide tuning range, low area and power consumption without degrading the phase noise as compared to existing VCO topologies in NTV regime. The improvement in the tuning range of the VCO is because of the change in body capacitance of the DTMOS configuration used in the VBRO. The change in the center frequency with PVT variations is compared with that of an NTV DRO. Post layout simulations have been performed on parasitic extracted netlist using HSPICE in industrial 65nm CMOS Process Design Kit (PDK). Our VBRO architecture has tuning range of 0.425 - 2.13 GHz with phase noise of -95dBc/Hz at 0.6V supply. The power consumption is only 127μW and the Figure Of Merit (FOM) is 164.96dBc/Hz.
Phase Noise Analysis of Separately Driven Ring Oscillators
(IEEE, 2022-08) Mishra, Neeraj
In this paper, for the first time, the phase noise analysis of a Multi-loop Skew based Single Ended Oscillator (MSSROs) is derived and validated. Compared to the three stages of conventional ring oscillators (CROs), SDROs provide an equivalent oscillation frequency with improved phase noise with increasing stages. The primary distinction between these two designs (SDRO and three-stage CROs) is the inherent skew offset between the PMOS/NMOS gates caused by the unique connection. This skew offset is the fundamental cause of delay cell noise suppression; the SDROs have loosely coupled oscillators that run concurrently, forming multiple 3-stages of separately driven Ring Oscillators. As a result, a shaping function is derived in terms of skew offset, and simulating these with varying skew offset results in suppressing behavior. Additionally, we derived phase noise for a skew-based design and validated it in PDKs of 180nm and 65 nm. We plotted the thermal (flicker) noise contribution and found that increasing the number of stages leads to an approximately 1-2 dB reduction in phase noise while maintaining the same NMOS/PMOS size ratio. Finally, a 2-3 dB reduction in phase noise is achieved in MSSROs by incorporating the shaping function into phase noise equations.
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies
(IEEE, 2015-06) Mishra, Neeraj
In stress enabled technologies the drive strength of multi-fingered (MF) transistors varies with the number of fingers (NF) because of Layout Dependent Effect (LDE). This is an important issue because MF transistors are widely used in integrated circuits. In this paper, we investigate performance variability issues in basic analog building blocks, such as current mirrors, common source amplifiers, and single ended differential amplifiers, designed using MF transistors. We observe that, due to the layout dependent channel mechanical stress, the analog performance parameters of these building blocks vary significantly. When the NF in MF transistors varies from one to seven, we observe that the copy current in cascode current mirrors vary by ~15%. For similar change in the NF there is ~22% and ~24% change in the bandwidth (BW) and the output resistance (R out ) respectively of an nMOS common source amplifier with pMOS current source load. We observe variations of ~32% in slew rate (SR), ~28% in BW, and ~12.4% in R out with the change in NF in a single ended differential amplifier. We model these variations as a function of NF in MF transistors since performance predictability in analog circuits is important. Finally, we designed a common source amplifier considering the impact of channel length on channel stress.
Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF
(Elsevier, 2023-12) Mishra, Neeraj
We propose a methodology to predict device-level variability (including aging) impact on the oscillation frequency () of an -stage ring oscillator (RO). This task is accomplished by creating a tool in a Python environment that uses our own developed variability-aware timing models of the CMOS inverter. Moreover, we use the model to foretell the impact of aging on the logical effort () of a CMOS inverter. Using the modified g, we resize ROs in an RO-based physical unclonable function (PUF) in the pre-layout stage to mitigate the impact of aging on the reliability of RO-PUF. The simulation is performed in the Cadence AMS environment using STMicroelectronics (STM) 28 nm CMOS process technology. With a one-time SPICE/aging simulation, the proposed methodology eliminates SPICE/aging simulation overhead for the prediction of variability impact on of a given -stage RO. This approach mitigates the impact of aging on the reliability of RO-PUF and provides a method for variability (including aging) aware design in the pre-layout stage.
Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis
(IEEE, 2024-05) Mishra, Neeraj
We propose switching activity factor-based effective current source model (SAFE) for aging-aware static timing analysis (STA), a new technique for estimating the timing performance of digital circuits. SAFE is based on the development of device-level variation-aware analytical timing models of stacked and multistage logic cells (commonly employed transistor topologies in a synthesized netlist of a random logic path), which drastically reduces the recharacterization efforts of the standard cells. The models developed are derived as a function of input transition time (TR) and load capacitance (CL) . The timing performance of a standard cell degrades with threshold voltage (Vth) degradation in a MOS device due to various aging mechanisms. SAFE, makes the entire STA process aging aware by updating its model coefficients with Vth degradation caused by aging. It is achieved by proposing a method for estimating Vth degradation under various stress conditions, including static, dynamic, and asymmetric, that applies to any process design kit (PDK). To consider asymmetric aging, we have developed a method to find effective switching activity factor (αeff) for N-stage stacked and N-stage parallel logic which is used to find the value of switching activity factor (α) at intermediate nodes in pipelined logic circuits. Our simulations are performed in Mentor Graphics Eldo SPICE environment using STMicroelectronics 28 and 65-nm CMOS process. The proposed technique provides a high-simulation accuracy (2.5% average error) when compared with SPICE simulations. Finally, we achieved a ~98.14% reduction in the required number of simulations using SAFE when compared with a completely SPICE/Aging simulation-based approach.
A Variation Aware Jitter Estimation Methodology in ROs Considering Over/Undershoots in NTV Regime
(IEEE, 2021-08) Mishra, Neeraj
A time-domain jitter estimation methodology considering process-voltage-temperature (PVT) variations of the single-ended ring oscillator (SERO) at an early stage of design is presented for near-threshold voltage (NTV) regime where non-linearities dominates. For the first time, the model accounts for the jitter due to the over/undershoot region which is critical in the NTV regime. Further, the model uses effective drive current, Ieff model. The Ieff is obtained considering the regions of device operation, instead of using only saturation current for jitter calculation. A time-domain jitter model is developed by considering the change in transition threshold points (TTPs) whose relative values are supply independent and Ieff of each region with the PVT variation, design parameters, and with the introduction of noise in the circuit. The model analyzes the effects of random (white noise) and deterministic (supply, substrate) noise in the NTV regime. This approach is physics/topology-based and is valid for different technologies. Post-layout simulations have been performed on parasitic extracted netlist using CADENCE and HSPICE in STM 65nm CMOS Process Design Kit (PDK) to validate the jitter model in the NTV regime.
Variation-Aware Prediction of Circuit Performance in Near-Threshold Regime Using Supply-Independent Transition Threshold Points
(IEEE, 2019-11) Mishra, Neeraj
Due to the highly variation-prone nature of the near-threshold voltage (NTV) circuits, it is critical to have design and performance models that consider process, voltage, and temperature (PVT) variations. However, in the NTV regime, the existing timing models are based on arbitrarily chosen VDD-dependent threshold points for effective current calculation that results in unreliability. In this article, an effective current delay model for an inverter operating in NTV regime is presented using supply-independent threshold points. The model is developed considering the input-output coupling capacitance and by relating the input and output currents of an inverter stage. This approach is physics-/topology-based and is valid for different technologies. This has been verified against HSPICE simulations and Synopsys Sentaurus 3-D technology computer-aided design (TCAD) simulations for STM 65-nm MOSFETs and 16-nm fin-shaped field-effect transistors (FinFETs), respectively, at different supply voltages, considering variation in threshold voltage and at different operating temperatures. The model predicts the transition delay values with an average (maximum) error of 3% (6%) and 4% (6%) for MOSFET and FinFET, respectively. Furthermore, the model is employed for digital buffer chain and single-ended ring oscillators (SEROs) for a wide range of supply voltages. Finally, we show an application of the model to calculate the change in the oscillation frequency of SERO with PVT variations and compare the same with the time-consuming Monte Carlo simulations.