Browsing by Author "Naidu, S.R."

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A convex programming solution for gate-sizing with pipelining constraints
(Springer, 2021-03) Naidu, S.R.
This paper proposes a novel geometric programming based formulation to solve a gate-sizing and retiming problem in the context of circuit optimization. The gate-sizing aspect of the problem involves continuous variables while the retiming problem involves the placement of registers in the circuit and can be naturally modeled using discrete variables. Our formulation is solved using first-order convex programming. We show promising experimental results on industrial circuits. We also investigate formally the computational complexity of the problem. To our knowledge, this is the first effort that solves this problem in a single optimization framework.
Parameter-importance based Monte-Carlo technique for variation-aware analog yield optimization
(IEEE, 2016) Naidu, S.R.
The Monte-Carlo method is the method of choice for accurate yield estimation. Standard Monte-Carlo methods suffer from a huge computational burden even though they are very accurate. Recently a Monte-Carlo method was proposed for the parametric yield estimation of digital integrated circuits [13] that achieves significant computational savings at no loss of accuracy by focusing on those statistical variables that have a significant impact on yield. We adapt this technique to the context of analog circuit yield estimation. The inputs to the proposed method are the designable parameters, the uncontrollable statistical variations, and the operating conditions of interest. The technique of [13] operates on a linear model of circuit variations. In our work we first convexify the nonlinear design constraints to obtain a convex feasible region. We then consider an accurate polytope-approximation of the convex feasible region by taking tangent hyperplanes at various points on the surface of the convex region. The hyperplanes give rise to a matrix of design variable sensitivities, which is then used to glean information about the importance of design variables for yield estimation. Finally the knowledge of which design variables are very important for yield estimation is used to allow the Monte-Carlo technique achieve a lower error compared to standard Monte-Carlo in the same amount of simulation time.
Speeding up Monte-Carlo Simulation for Statistical Timing Analysis of Digital Integrated Circuits
(IEEE, 2007) Naidu, S.R.
This paper presents a pair of novel techniques to speed-up path-based Monte-Carlo simulation for statistical timing analysis of digital integrated circuits with no loss of accuracy. The presented techniques can be used in isolation or they could be used together. Both techniques can be readily implemented in any statistical timing framework. We compare our proposed Monte-Carlo simulation with traditional Monte-Carlo simulation in a rigorous framework and show that the new method is up to 2 times as efficient as the traditional method
Statistical Timing for Parametric Yield Prediction of Digital Integrated Circuits
(IEEE, 2006) Naidu, S.R.
Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. The three methods are complementary in that they are designed to target different process variation conditions that occur in practice. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Timing analysis results in the face of statistical temperature and V dd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results
Variation-aware parameter based analog yield optimization methods
(ACM Digital Library, 2019-04) Naidu, S.R.
The problem of yield estimation and optimization of analog circuits is addressed in this paper. Given convex design-space constraints that define the feasible region for the design, we first linearize the feasible region by approximating it with linear constraints. Using the linear constraints approximating the feasible region, we make primarily two contributions in this paper--first we use the concept of parameter importance, introduced in Naidu (20th International conference on VLSI design, 2007. Held jointly with 6th international conference on embedded systems. IEEE, pp 265---270, 2007) and expanded on in Kondamadugula and Naidu (ACM Great Lakes symposium on VLSI. IEEE, pp 452---457, 2016), to partition the design space variables into those that affect yield a lot, and those that have only a marginal impact, and then use this information to speed-up a Monte-Carlo method that searches for a high-yield design point. Specifically, a two-step sampling procedure is devised for the variables where the outer-most loop is dedicated to the "weak" variables while the inner loop is dedicated to the "strong" variables. Thus the given simulation budget is then disproportionately directed towards those design space parameters deemed more important. Since there are likely be only a few variables that impact yield greatly, we can choose to use low-dimensional quasi-Monte-Carlo sequences for sampling in the inner loop which is an added benefit of our technique. For each sample design point, the Monte-Carlo algorithm would need to calculate yield using the Cadence yield estimation tool. This is a costly procedure. For the second application of the concept of parameter importance, we propose a fast procedure for calculating yield that works with a linear approximation of the feasible region, and uses design space information to speed up the calculation of yield. We compare our methodology with the standard one using the Cadence circuit simulator environment in 180 nm technology and show that we obtain superior results in the same amount of simulation time.