Browsing by Author "Shekhar, Chandra"

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A 12.11 mW, 99 pJ/Conv.-Step SAR ADC with Optimal Power Efficiency for IoT
(IEEE, 2024-12) Gupta, Anu; Shekhar, Chandra
This brief presents a capacitive charge scaling DAC architecture with a two-phase non-overlapping clocking scheme to make an energy-efficient Successive Approximation Register (SAR) data converter for Internet-of-Things (IoT) applications. The proposed architecture comprises a Track & Hold (T/H), a Modified Strong Arm Latch comparator (MSAL), a SAR Control logic, and a digital-to-analog (D/A) converter. The proposed work is simulated using Cadence Virtuoso in TSMC 180 nm and achieves a minimum sampling rate of 1 MS/s and power consumption of 12.11 mW. To address the effects of process variations and mismatches on ADC performance, this paper conducts a thorough 500-point Monte Carlo (MC) simulation of the proposed SAR ADC circuit. The measured results show a Signal-to-Noise Ratio (SNR) of 47.81 dB, a Spurious-Free Dynamic Range (SFDR) of 54.32 dB, and ENOB of 7.65 Bits.
Admission Control Policy of Maintenance for Unreliable Server Machining System with Working Vacation
(Springer, 2017-03) Shekhar, Chandra
This investigation is concerned with the performance modeling of machining system operating under the admission control F-policy and server working vacation policy. The repair of failed machines is provided by an unreliable server, who also renders the service with the slower rate rather than completely terminating the service during the vacation period. The failed machines are allowed to enter the system till the system capacity (K) is full; then after failed machines are not allowed to join the system until the system size again decreases to the prespecified threshold level ‘F’. At that instant, the server takes start-up time in order to start allowing the failed machines to enter into the system for the repair job. Numerical method based on successive over-relaxation is applied to obtain the steady-state probabilities and various performance indices including the cost function. The numerical simulation is performed to explore the sensitivity of the system indices with respect to various parameters. Quasi-Newton method and direct search method are used to determine the optimal service rate and threshold parameter.
Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis
(Springer, 2021-07) Asati, Abhijit; Shekhar, Chandra
This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a novel high-level synthesis design method, which reduces pessimism associated with bit-width constraints in synthesis for inputs, outputs, and intermediate data nodes. MATLAB HDL coder generated Register Transfer Level (RTL) code was implemented on Xilinx Kintex 7 using Vivado software. The obtained results are superior to those of previous implementations for exact filter specifications. We also performed an RTL simulation for the filter and compared the functional verification results with a golden double-precision implementation in MATLAB. The results suggest that constraining the bit width and pessimism reduction has less than 1% impact on the filter accuracy within limits specified by architecture specifications.
Area-optimal FPGA implementation of the YOLO v2 algorithm using High-Level Synthesis
(IEEE, 2020) Asati, Abhijit; Shekhar, Chandra
Field-programmable gate arrays (FPGAs) have been used as pre-silicon validation platforms in VLSI designs. In this paper, we propose a FPGA-based you-only-look-once (YOLO) v2 object detector implementation that provides better performance in terms of speed, achieves higher accuracy, and requires fewer resources compared with the alternatives. It is constructed using a convolutional deep neural network (CNN). We apply high-level synthesis (HLS) to model and optimize the implementation using multiple directives, such as pipelining, loop unrolling, in-lining, etc. The proposed YOLO v2 design is implemented on a Xilinx Zynq xc7z020clg484-1 device. We run simulations to test its functionality using an xSim simulator. The proposed implementation not only runs faster, but it utilizes an order of magnitude fewer resources than available implementations in the literature.
Assessment of the Yoga on the Status of the Physical Fitness among Children of the Residential School
(IJLTEMAS, 2015-03) Shekhar, Chandra
In this article, we primarily study current health related physical fitness and health enhancing physical activity of residential school children of Birla Education Trust, Pilani, India. 276 school children, aged 8 to 14 are selected from three residential public schools of BET, Pilani. The present study is undertaken to show the effects of yoga and prayanam on growing children by comparing the PFI test performance of residential school children.
Bayesian modeling of repairable systems with imperfect coverage and delayed detection dynamics
(Wiley, 2025-02) Shekhar, Chandra
In this research article, we thoroughly examine the dynamics of a repairable system, emphasizing a two-unit configuration through a Bayesian perspective. The study integrates diverse prior distributions to model the uncertainty of unknown parameters, incorporating the coverage factor as a probabilistic measure of successful recovery from operational unit failures. The temporal characteristics of unit failure and repair are modeled using exponential distributions, ensuring analytical tractability and robustness. The repair process is bifurcated into two distinct phases: fault detection and location, followed by actual repair, with each phase governed by exponential distributions. Additionally, recovery and reboot times for failed units are also characterized by exponential distributions to maintain consistency in the probabilistic model. To address parameter uncertainty, we adopt a Bayesian methodology, enabling a comprehensive evaluation of system performance metrics. Monte Carlo simulations are employed to derive posterior distributions for critical parameters, including the mean time to system failure and steady-state availability, offering deeper insights into the system's reliability profile. To validate the efficacy of the proposed methodology, extensive numerical experiments are conducted, providing a robust confirmation of the analytical models and computational techniques.
A brief review on retrial queue: Progress in 2010-2015
(IJASER, 2016-01) Shekhar, Chandra
The present survey is based on the principle of retrials in queueing theory i.e. the customers who repeatedly try to avail the services from the server, on finding dejection, because of the inactivity of the server to provide service at an instant of selection from the queue. A bunch of work has previously been done on this front from past since it is realistic phenomena of many service system. The current investigation aims to present a brief review of the major works done on retrial queueing systems in recent years. The bibliography consists of research articles which were published in journals of repute during the period 2010-2015. In addition to the above references, an exhaustive list of books and survey papers on retrial queueing systems is also prepared so as to provide a detailed enough catalog for further understanding and research in retrial queueing domain. We have classified the journal papers according to the year of publishing. The aim of the present study is to turn up at a broad enough for a collection of important results in the theory of retrial queueing systems and their applications in solving several realistic problems. The main contribution is the bibliography of recent papers and books collected from different databases and private sources. At last, we have arranged some of the references according to the classification based on analysis and solution technique. The author(s) hope that this survey paper could be of help to learners contemplating research on retrial queues.
Comparative Analysis of D/A Converter Architectures for SAR ADC
(IEEE, 2024-02) Gupta, Anu; Shekhar, Chandra
This study gives an in-depth analysis of the architectures utilized in the analog-to-digital conversion process. The paper encompasses the design, performance, and suitability of the binary-weighted (charge distribution), R-2R ladder, and C-2C Digital-to-Analog (D/A) Converter architectures. This paper's discussed D/A converter architectures are simulated through the cadence tool using 180 nm CMOS technology. Based on comparative performance analysis, the C-2C D/A converter gives optimum results in terms of power, speed, DNL, INL, and settling time while maintaining its resolution. C-2C D/A converter reported a 63.15% improvement in power consumption compared to R-2R DAC, DNL, and INL errors below 0.01 LSB.
Comparative Analysis of Phase/Frequency Detector in a Complete PLL System
(IEEE, 2023) Gupta, Anu; Shekhar, Chandra
In many integrated radio frequency (RF) transceivers, the phase-locked loop (PLL) serves as a frequency synthesizer. This work goes to test various different phase/frequency detector blocks with a standard charge pump and Voltage controlled oscillator design. These include the comparison of different phase-frequency detectors (PFD) based upon D-flipflops, latches (Latch PFD) & pass transistors (PTPFD) to the more complex Pre-charged PFD. The best results of the PFDs in the PLL system in order are Pre-charge PFD, PT-PFD, Latch PFD and D-flipflop PFD. A charge pump PLL (CPLL) with a frequency range of [80 MHz -800 MHz] is simulated using Cadence Virtuoso (Spectre) at 180nm technology (scl\_pdk) with 1.8 V supply voltage. The phase noise of the VCO is less than -50dBc/Hz at 10MHz and is closer to 110dBc/Hz at 1GHz.
Comparative and performance analyses of unreliable server queues
(CRC Press, 2024) Shekhar, Chandra
Queue-based scenarios with server breakdowns have become an exciting topic for queueing theorists, researchers, and practitioners in past decades. These queueing systems are generally used in many realistic waiting line models in our day-to-day life, such as computer and communication systems, production systems, transportation systems, flexible manufacturing systems, etc. Several scholars and researchers have worked on queueing systems with server breakdowns and provided significant results during the last few decades. Gaver [1] and Shogan [2] investigated queueing systems with server breakdowns and provided explicit expressions of several queuing-based system performance indicators. Jayaraman et al. [3] studied a bulk queueing system with state-dependent arrival rate and server breakdown. In 2004, Ke [4] discussed a bi-level control policy for the batch arrival queue with an early start-up and unreliable server. Later, Jain and Agrawal [5] considered an https://www.w3.org/1998/Math/MathML" display="inline"> M X / M /1 https://www.w3.org/1999/xlink" xlink:href="https://s3-euw1-ap-pe-df-pch-content-public-p.s3.eu-west-1.amazonaws.com/9781003481263/3627ff2f-b685-486a-bdfb-379751e6ddcc/content/inline-math8_1.tif"/> queueing system with multiple breakdown states of the unreliable server under https://www.w3.org/1998/Math/MathML" display="inline"> N https://www.w3.org/1999/xlink" xlink:href="https://s3-euw1-ap-pe-df-pch-content-public-p.s3.eu-west-1.amazonaws.com/9781003481263/3627ff2f-b685-486a-bdfb-379751e6ddcc/content/inline-math8_2.tif"/> -policy. In the same year, Wang and Yang [6] investigated a controllable queueing system with an unreliable server. They illustrated many interesting numerical experiments for the optimal analysis using the semi-classical optimizer, the Quasi-Newton method. For more in-depth analysis, one can refer to the research findings in (cf. [7–15]) and references therein. Recently, Ke et al. [16] studied a feedback retrial queue with balking behavior of the customer and unreliable server and developed a cost optimization problem determining the optimal parameter setting under the stability condition using Probability Global Search Lausanne (PGSL) approach. A retrial queueing system with a finite number of sources and customers collision is discussed by Nazarov et al. [17]. They proved that the limiting probability distribution of the number of customers in the queueing system follows a Gaussian distribution.
A comprehensive survey on data converters for IOT applications: scope, issues, and future directions
(IEEE, 2025-03) Gupta, Anu; Shekhar, Chandra; Chamola, Vinay
Data converters significantly contribute to efficient and accurate data processing in Internet of Things (IoT) systems. As IoT expands into agriculture, industrial automation, and healthcare (AIH), precise and low-power data conversion has become crucial to support longer battery life and reliable performance in IoT devices. Efficient data converters are key to reducing energy use, especially in components like comparator circuits, which consume significant energy in successive approximation register analog-to-digital converters (SAR ADCs). This survey provides an in-depth review of recent developments in low-power data converter design, examining techniques that help reduce power consumption at various stages. It emphasizes advancements, such as energy scaling, dynamic voltage references, and architectural optimizations that enhance efficiency without compromising performance. A specific analysis of emerging technology trends, such as the application of machine learning in data converter design, is explored to stimulate further innovation. Machine learning (ML)-based optimization, including adaptive calibration, noise reduction, and real-time performance optimization, presents new opportunities for enhancing efficiency and accuracy while addressing critical design constraints in IoT applications. While quantum encryption offers promising advancements in securing IoT data transmission, a broader security perspective beyond encryption is necessary, including concerns, such as attack detection and data integrity, ensuring the robustness of IoT systems. This review also examines latency, signal integrity, and accuracy issues, offering a roadmap for next-generation converter designs and reducing power consumption in data converters, which are fundamental to enhancing the performance and lifespan of IoT devices.
Congestion analysis of finite tandem queueing network
(IEEE, 2023) Shekhar, Chandra
This paper introduces a focused model for analyzing congestion in finite tandem networks, a crucial aspect in queueing theory with far-reaching implications for system efficiency. By examining job flow through nodes, Node-1 and Node-2, it reveals intricate relationships between latent and processing times, exploring system dynamics. Incorporating Poisson arrivals, balking, and diverse processing mechanisms, the model encompasses both direct job progression and potential balking, offering a comprehensive view. Additionally, it accounts for waiting job processing, reneging, and Node-2's breakdown vulnerabilities and recovery. The model's independence of processes amplifies its depth. This analysis enriches our understanding of finite tandem queueing networks and their congestion intricacies. The model aids in optimal resource allocation and system design, enhancing congestion and delay management in practical settings like transportation and communication networks. It forms a foundation for informed operational strategies, bolstering customer satisfaction and resource utilization in complex service systems
Cost analysis of a finite capacity queue with server failures, balking, and threshold-driven recovery policy
(IJMEMS, 2024-07) Shekhar, Chandra
The study is on the cost dynamics which is concerned with finite queues in particular to susceptibility to server outages, threshold-driven recovery and Catastrophic events, but main focus is on balking behaviour of the customers. A thorough investigation of the financial implications of interruptions and efficacy to recovery strategies is done and to alleviate the impact of breakdowns, disasters and customer refusals the queue system designs through empirical research is conducted. Various recovery policies have been compared with the existing thresholds, and the study further endeavors to categorize the cost-effective approach to mitigate the economic concerns of server failures and catastrophic incidents. The study brings discernments on the expected development in the management of the queuing system along with the assistance in complete decision-making in cost efficiency and enhancement of the complete system performance.
Design & Analysis of Performance-efficient Comparator for IoT Application
(IEEE, 2022) Shekhar, Chandra; Gupta, Anu
The regenerative latch comparator prototype for high-speed up to 1 Giga Hertz analog-to-digital conversion is shown in this article. Cascading structure of different modules makes the proposed comparator a suitable choice for various converters like SAR, Pipelined, Flash, etc. The proposed comparator achieves efficiency in terms of propagation latency, power consumption, and area as compared to the present state of the art mentioned in this work. Additionally, it uses the cadence schematic editor tool to illustrate how the performance of a comparator changes depending on its common-mode voltage (Vcm) and input (Vid) on TSMC 180 nm CMOS technology.
Design and Analysis of Modified Strong Arm Latch Comparator with Reduced Kickback Noise
(Springer, 2024-10) Gupta, Anu; Shekhar, Chandra; Chaturvedi, Nitin
This research paper introduces three techniques to reduce kickback noise in the Strong Arm Latch Comparator (SAL). The first technique focuses on utilizing high clock power and generating two clocks with different duty cycles. While initially addressing the issue by applying a single clock to the kickback-reducing circuit, the reduction of kickback noise did not meet the desired level. To overcome this limitation, a new design is proposed, incorporating a delay in the programmability of the kickback-reducing circuit, which effectively eliminates the need for kickback and clock requirements. A comparative study is conducted, evaluating all the designs, including the proposed design, based on power, delay, and analysis of various types of noise. Results show that the proposed technique outperforms other kickback-reducing designs in terms of propagation latency, power consumption, and kickback currents. Additionally, the impact of a comparator’s common-mode voltage (Vcm) on its performance in TSMC 180 nm CMOS technology is demonstrated using the Cadence Schematic Editor tool.
Design and implementation of successive approximation register data converter
(AIP, 2024) Gupta, Anu; Chaturvedi, Nitin; Shekhar, Chandra
Analog-to-Digital Converters (ADCs) serve as crucial interfaces between the analog and digital domains, facilitating the transformation of analog signals into digital representations. Data processing in the digital domain presents distinct performance advantages over the analog domain in particular aspects. To facilitate the reverse conversion of processed digital signals back into the real-world signal domain, Charge Redistribution Digital-to-Analog Converters (DACs) are employed. DACs also play a pivotal role as significant components in specific ADC architectures, such as the Successive Approximation Register (SAR) Analog-to-Digital (A/D) Converter. Moreover, a Strong-Arm Latch Comparator has been utilized to compare the input analog voltage with the output voltage of the DAC. This paper primarily focuses on the implementation and thorough analysis of the SAR-ADC. The study includes calculatinganalog voltages’ precise range and corresponding digital outputs. The maximum Differential Non-Linearity (DNL) error, offset error, and full-scale error for this specific SAR-ADC have been measured and found to be 0.28*LSB, 0.2*LSB, and 0.22*LSB, respectively. The results presented in this paper provide valuable insights into the performance and accuracy of the SAR-ADC, paving the way for further advancements and applications in the domain of A/D conversion.
Different variants of unreliable server: An economic approach
(CRC Press, 2023) Shekhar, Chandra
This chapter investigates a single-server finite-capacity service system in a Markovian environment for different variants of unreliable servers. Three diverse mathematical models are discussed using the queueing-theoretic approach and nomenclatures: customers’ impatience, working breakdown, service pressure condition, and threshold-based recovery policy. The Chapman–Kolmogorov differential-difference equations for each model are established, and the matrix method is employed to exhibit the steady-state queue-size distribution. In addition, explicit closed-form expressions of various system performance measures are provided, which are used to construct an expected total cost function. We also develop a cost optimization problem to determine the optimal operating policy at a minimum expected cost of the service system. As a classical optimizer, the quasi-Newton method is employed to ascertain the solution to the developed cost optimization problem. Furthermore, a comparative analysis is performed between each developed model for the detailed study using various combinations of system design parameters and default cost elements. Finally, several graphs and tables provide managerial insights to understand the research findings better.
Double orbit finite retrial queues with priority customers and service interruptions
(Elsevier, 2015-02) Shekhar, Chandra
The present study deals with the double orbit finite capacity retrial queues with unreliable server. The system facilitates the arrival of two types of customers known as priority and non priority customers and can hold a maximum of L priority customers and K non-priority customers as per its capacity. The priority customers are served prior to the non-priority customers. Moreover, the server is unreliable which may breakdown while servicing either priority or non-priority customer. The failed server is sent for repair following threshold recovery policy to become as good as earlier. Both transient as well as steady state analysis of the model has been done using by matrix method. Various performance measures including queue length, reliability metrics, long run probabilities, etc. have been obtained using various state probabilities. The application of the model to cellular radio network has been discussed. The cost function has been constructed and optimized using meta heuristic approach. The sensitivity analysis of various performance indices has been performed as an illustration.
Dual channel addition based FFT processor architecture for signal and image processing
(ACM Digital Library, 2009-12) Gupta, Anu; Shekhar, Chandra; Asati, Abhijit
This paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. This approach reduces the number of required complex multiplications compared to a normal discrete Fourier transform. Since multipliers are very power hungry elements in VLSI designs, they result in significant power consumption. So, the complex multiplication operations are realised using shift-and-add operations. The proposed algorithm performs all intermediate addition operation using a novel dual channel addition technique, which avoids carry propagation delay. Only in the last stage, carry look ahead adders are used to give final result. This dual channel addition algorithm reduces the critical delay path by 42% and 38.29% as compared to traditional and Maharatna approach respectively.
Effect of thickness on the properties of ZnO thin films prepared by reactive RF sputtering
(Springer, 2018) Gupta, Navneet; Kandpal, Kavindra; Shekhar, Chandra
This work reports structural and electrical properties of ZnO thin film deposited by reactive RF sputtering at the room temperature, for thin film transistor (TFT) applications. To study the thickness dependent effect, ZnO thin film of thicknesses 100, 200 and 800 nm were deposited over p-type silicon substrate. Structural properties of thin films have been characterized using X-ray Diffraction (XRD) and Atomic Force Microscopy (AFM). XRD analysis of 100 and 200 nm thick films shows dominant cubic phase of ZnO along with small presence of ZnO2, while; XRD analysis of 800 nm thick film confirms strong c-axis growth of wurtzite (W) ZnO. The XRD result confirm the polycrystalline nature of the thin film and shows that crystallinity improves with the film thickness. The AFM results confirm high step coverage of deposited thin films. From the thermionic transport model across the grain boundary it was observed that with an increase in film thickness mobility of carriers increases. The sheet resistance of undoped 100 and 200 nm ZnO film is found to be approximately 7 × 1011 Ω/□; while, the sheet resistance of 800 nm thick ZnO film shows almost 10 time reduction to 6.025 × 1010 Ω/□, owing to its improved crystallinity.