BITS Faculty Publications

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    Dual channel addition based FFT processor architecture for signal and image processing
    (ACM Digital Library, 2009-12) Gupta, Anu; Shekhar, Chandra; Asati, Abhijit
    This paper presents a novel fixed-point 16-bit word-width 16-point FFT/IFFT processor architecture designed primarily for the signal and image processing application. The 16-point FFT is realised by using Cooley-Tukey decimation in time algorithm. This approach reduces the number of required complex multiplications compared to a normal discrete Fourier transform. Since multipliers are very power hungry elements in VLSI designs, they result in significant power consumption. So, the complex multiplication operations are realised using shift-and-add operations. The proposed algorithm performs all intermediate addition operation using a novel dual channel addition technique, which avoids carry propagation delay. Only in the last stage, carry look ahead adders are used to give final result. This dual channel addition algorithm reduces the critical delay path by 42% and 38.29% as compared to traditional and Maharatna approach respectively.
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    A Novel Technique for Improvement of Power Supply Rejection Ratio in Amplifer Circuits
    (IEEE, 2009-12) Gupta, Anu; Chaturvedi, Nitin; Asati, Abhijit
    Most of the time, power supplies fail to provide a constant voltage supply and some external voltage signal may override on the power supply giving unwanted fluctuation at the output node. This paper discusses 3 techniques to improve the power supply rejection ratio (PSRR) in amplifier circuits. (1) Cascoding technique - cascoding increases the gain from input node to output node giving high PSRR values at low frequency. (2) Feedback technique - a negative feedback in circuits generally improves PSRR since it ensures that output follows the input signal and any other external disturbance is rejected. (3) Designing an additional circuit which could nullify the effect of the voltage gain from the power supply to the output node.
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    A Review on Ultra Low Power Design Technique: Subthreshold Logic
    (IJCST, 2013) Gupta, Anu; Asati, Abhijit
    Rapid increases in chip complexity, increasingly faster clocks and proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a system determines its heat dissipation as well as battery life. For some digital systems, power consumption has become the most critical design constraint. To satisfy the low power requirement one of the best technique sub-threshold logic is being introduced. This paper presents a complete review of recent research and explores all aspects/ constraints of subthreshold logic design technique. The paper explores basics of subthreshold, sources of power dissipation, challenges in subthreshold design, optimization methodology and various types of techniques which are currently used to implement ultra low power based circuits using subthreshold logic