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Efficient ASIC Implementation of Artificial Neural Network with Posit Representation of Floating-Point Numbers
(Springer, 2023-07) Gupta, Anu; Gupta, Rajiv
This paper presents a low-power ASIC architecture of a feedforward Artificial Neural Network using Posit representation. The ASIC Posit shows 50% improvement over ASIC using IEEE 754 format in terms of Power and Silicon Area and is also 13% faster while achieving the same accuracy. The same design using the FPGA platform consumes more power than the ASIC design. The designs are done using Cadence RTL Encounter with TSMC 180 nm technology node.
Low-cost Artificial Intelligence Enhanced Hardware Design for Data Augmentation
(IEEE, 2023) Gupta, Rajiv; Gupta, Anu
This paper presents a novel low-cost hardware implementation of data augmentation using artificial neural networks for a low-power, low-cost Water Quality Indexing application. Multilayer Perceptron (MLP) feedforward network with backpropagation learning has been designed to predict the data of DO and EC using pH and ORP as the input vector. This reduces the requirement for costly sensor electrodes, decreasing the design's cost. The design has been implemented on both ASIC and Embedded platforms. The Augmentation ANN predicts DO and EC with a 98% accuracy rate and achieves a 92% reduction in cost. The results have been presented and compared with standard WQI device.