BITS Faculty Publications
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Item DAAS: differential aging-aware STA for precise timing closure with reduced design margin(IEEE, 2025-08) Mishra, NeerajThis article introduces DAAS, a Differential Aging-Aware Static Timing Analysis methodology built upon an Effective Current Source Model (ECSM). The primary objective is to achieve precise timing closure for digital integrated circuits while minimizing design margins. To achieve this goal, we employ a one-time aging simulation using a single MOS device-based approach. This approach estimates the change in threshold voltage (Vth) denoted by (Vth) in a MOS device under diverse operating conditions, such as supply voltage and temperature, in the presence of aging. The estimated value of (Vth) is then used to update the model coefficient of timing models for various combinational gates. These updated models are utilized to generate differential aging-aware standard cell library data in an industry-standard Liberty format. This data can be seamlessly integrated into common STA environments like Synopsys PrimeTime, facilitating the estimation of timing closure for designs with different blocks operating at varying voltages and temperature conditions. The proposed methodology eradicates the need for circuit-level aging simulation to generate differential aging-aware standard cell library data. It demonstrates an average error of 2.5% compared to conventional aging simulation on standard cells using the STMicroelectronics (STM) 28 nm CMOS process. Furthermore, the method significantly reduces the required number of SPICE/aging simulations by approximately 99.984% to generate differential aging-aware standard cell library characterization data. Further, we demonstrate the versatility of the proposed DAAS methodology for the generation of standard cell library data in the case of PDK migration and different device variants without performing full SPICE-level simulations.Item Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort(IEEE, 2022-12) Mishra, NeerajA static timing analysis (STA) methodology based on an effective current source model (ECSM) is proposed for the first time for estimating the aging-aware path-level timing performance and its impact on the logical effort of a CMOS inverter for digital timing closure in pre-stress and post-stress conditions. Degradation in the threshold voltage (Vth) of PMOS occurs due to temporal variability mechanisms (aging), such as negative bias temperature instability, resulting in delay degradation of a standard cell. Therefore, we proposed a technique to make the STA process aware of this degradation by developing device-level variation aware (with aging) timing models of CMOS inverters to represent threshold-crossing points (TCPs) in an ECSM.libs file as a function of stress time ( t ). A device-level approach for Vth degradation into different aging conditions, such as static and dynamic, is developed for a given process design kit to update TCPs in a (.libs) file as a function of t . A python-based tool is being developed to estimate the path-level timing performance of digital circuits in pre- and post-stress conditions. Again, we developed a technique for relating the inverter’s logical effort with t to resize a near-critical path in pre-stress conditions for achieving digital timing closure in pre- and post-stress conditions. The verification and validation of the proposed model with different benchmark circuits are performed using a parasitic extracted netlist in the Eldo SPICE environment with the 65-nm CMOS process technology. Finally, our model reduces the number of SPICE/Stress simulations by 98.13% compared to the previously reported only simulation-based techniques.Item Prediction of variation aware FOSC in ring oscillators (ROs) to mitigate the impact of aging on RO-PUF(Elsevier, 2023-12) Mishra, NeerajWe propose a methodology to predict device-level variability (including aging) impact on the oscillation frequency () of an -stage ring oscillator (RO). This task is accomplished by creating a tool in a Python environment that uses our own developed variability-aware timing models of the CMOS inverter. Moreover, we use the model to foretell the impact of aging on the logical effort () of a CMOS inverter. Using the modified g, we resize ROs in an RO-based physical unclonable function (PUF) in the pre-layout stage to mitigate the impact of aging on the reliability of RO-PUF. The simulation is performed in the Cadence AMS environment using STMicroelectronics (STM) 28 nm CMOS process technology. With a one-time SPICE/aging simulation, the proposed methodology eliminates SPICE/aging simulation overhead for the prediction of variability impact on of a given -stage RO. This approach mitigates the impact of aging on the reliability of RO-PUF and provides a method for variability (including aging) aware design in the pre-layout stage.Item Switching Activity Factor-Based ECSM Characterization (SAFE): A Novel Technique for Aging-Aware Static Timing Analysis(IEEE, 2024-05) Mishra, NeerajWe propose switching activity factor-based effective current source model (SAFE) for aging-aware static timing analysis (STA), a new technique for estimating the timing performance of digital circuits. SAFE is based on the development of device-level variation-aware analytical timing models of stacked and multistage logic cells (commonly employed transistor topologies in a synthesized netlist of a random logic path), which drastically reduces the recharacterization efforts of the standard cells. The models developed are derived as a function of input transition time (TR) and load capacitance (CL) . The timing performance of a standard cell degrades with threshold voltage (Vth) degradation in a MOS device due to various aging mechanisms. SAFE, makes the entire STA process aging aware by updating its model coefficients with Vth degradation caused by aging. It is achieved by proposing a method for estimating Vth degradation under various stress conditions, including static, dynamic, and asymmetric, that applies to any process design kit (PDK). To consider asymmetric aging, we have developed a method to find effective switching activity factor (αeff) for N-stage stacked and N-stage parallel logic which is used to find the value of switching activity factor (α) at intermediate nodes in pipelined logic circuits. Our simulations are performed in Mentor Graphics Eldo SPICE environment using STMicroelectronics 28 and 65-nm CMOS process. The proposed technique provides a high-simulation accuracy (2.5% average error) when compared with SPICE simulations. Finally, we achieved a ~98.14% reduction in the required number of simulations using SAFE when compared with a completely SPICE/Aging simulation-based approach.