BITS Faculty Publications
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Item The Impact of Channel Engineering on the Performance Reliability and Scaling of CHISEL NOR Flash EEPROMs(IEEE, 2003-09) Rao, V. RamgopalThe programming performance, cycling endurance and scaling of CHISEL NOR flash EEPROMs is studied for two different (halo and no-halo) channel engineering schemes. Programming speed under identical bias, bias requirements under similar programming time, cycling endurance and drain disturb are compared. The scaling properties of programming time (at a fixed bias), bias (at a fixed programming time) and program/disturb margin are studied as cell floating gate length is scaled. The relative merits of these channel engineering schemes are discussed from the viewpoint of futuristic CHISEL cell design.Item Device-circuit co-design for high performance level shifter by limiting quasi-saturation effects in advanced DeMOS transistors(IEEE, 2016) Rao, V. RamgopalThis paper presents a device-circuit co-design methodology for a DeMOS 5V GHz-speed high voltage level shifter. The limiting quasi-saturation effect is addressed by a codesign methodology. The co-design methodology is applied to the STI-DeMOS in a calibrated setup using experimental data. As a result, a 15% improvement in the speed is achieved for a high-performance level shifter circuit.Item Novel hydroxy-phenyl phosphorus porphyrin self-assembled monolayers for conformal n-type doping in Finfets(IEEE, 2016) Rao, V. RamgopalA controllable and selective process for doping is essential for current CMOS technology, and with the advent of FinFETs, necessity for conformal doping has become inevitable. In this work, we demonstrate formation of novel phosphorus porphyrin self-assembled monolayers(SAMs) on silicon substrate to dope silicon with phosphorus (n-type doping). Detailed physical characterization of SAMs formed on silicon is done using contact angle, FTIR, UV-Vis, etc. The doping is confirmed using SIMS and four-probe measurement (sheet resistance). MISCAP devices, pn junction diodes using the above technique are fabricated and characterized using capacitance-voltage (CV) and current-voltage (IV) measurements. SAM layer is utilized for doping in 3D fin like structures.