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    An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications
    (Springer, 2019-11) Vidhyadharan, Sanjay
    Adiabatic circuits are ideally suited for implementing RFID tags and biomedical sensors due to their ultra-low power requirements. This paper presents a novel Gate Overlap Tunnel FET (GOTFET) based Advanced Adiabatic Logic which consumes upto 67% lower power than the equivalent CMOS based Symmetric Pass Gate Adiabatic Logic (SPGAL) which is the most power efficient adiabatic topology reported in recent literature. The basic building blocks of the proposed GOTFET Adiabatic Logic (GOTAL) circuits are the innovative Complementary GOTFETs (CGOT) which have twice the on state currents Ion and one order lower off state currents Ioff than the corresponding MOSFETs having same width at the same technology node. In addition to the novel devices, the novelty in the proposed design is the usage of specially engineered low threshold voltage Vt GOTFETs for minimizing non-adiabatic losses and completely avoiding the unnecessary complexity involving the generation of discharge pulse in the resetting clock circuit. Adiabatic inverter, NAND and NOR gates implemented using the proposed GOTAL circuits consume up to two orders (97%) lower power than the corresponding conventional static CMOS circuits at the same frequencies of operation under the same capacitive loads. Although adiabatic circuits are usually designed for low frequency operation, GOTAL circuits may also be used at higher frequencies owing to the improved frequency response of the CGOT devices.
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    An innovative ultra-low voltage GOTFET based regenerative-latch Schmitt trigger
    (Elsevier, 2020-10) Vidhyadharan, Sanjay
    This paper introduces an innovative Gate-Overlap Tunnel FET (GOTFET) device which is an advanced TFET engineered to yield around double the on current Ion, while the off current Ioff remains around an order lower, than that of an analogous equally-sized MOSFET at the same technology node. Higher Ion: Ioff ratio and steeper sub-threshold slope of the proposed GOTFETs make them ideal candidates for ultra-low voltage applications like Schmitt trigger circuits. Considering the superior performance of the proposed GOTFET devices, simply replacing the MOSFETs with the proposed GOTFETs in conventional Schmitt trigger circuit significantly reduces the delays and static power consumption of the circuit as expected. At 0.4 V power supply voltage, there is 91.7% improvement in Power Delay Product (PDP) for Complementary GOTFET (CGOT) based conventional Schmitt trigger as compared to CMOS conventional Schmitt trigger for the same hysteresis width of 120 mV. In order to further minimize the dynamic power, a novel CGOT regenerative-latch Schmitt trigger design has also been presented in this paper for the first time, which further reduces the total (static + dynamic) power consumption and delays of the conventional Schmitt trigger circuit. The overall PDP in the proposed CGOT regenerative-latch based Schmitt trigger has been demonstrated to be merely 1.9% of (98.1% lower than) the PDP in corresponding CMOS conventional design.
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    An Efficient Ultra-Low-Power and Superior Performance Design of Ternary Half Adder Using CNFET and Gate-Overlap TFET Devices
    (IEEE, 2021-01) Vidhyadharan, Sanjay
    This paper presents a novel ultra-low power yet high-performance device and circuit design paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs (GOTFETs) and Carbon Nanotube FETs (CNFETs). One of the distinguishing novelty reported in this work is the introduction of an innovative GOTFET device, which exhibits more than double the on-currents I on and less than 1/10 th the off-currents I off of equivalent, equally-sized mosfets at the same technology node. Most of the ternary logic designs reported earlier in the literature encode ternary bits into binary for combinational functionality and then use an Encoder to get back ternary output. Unlike the earlier designs, this paper presents a novel and significantly more efficient approach of directly designing ternary logical functions with Low V t Transistors (LVT) and High V t Transistors (HVT) using CNFET and GOTFET technologies. The new approach simplifies the design and reduces the required transistor count & interconnects, thereby reducing the delays and power consumption. The proposed Ternary Half Adder (THA) circuit, designed using CMOS, enables a 52% reduction in transistor count compared to the conventional CMOS designs available in the literature. The THA implemented with CNFET exhibits 27 ps (87% lower delay than similar CMOS design and consumes 2.4 μW power (11% lower than CMOS). On the other hand, CGOT THA exhibits 101 ps (51% lower delay than similar CMOS design) and consumes merely 1.26 μW power (53% lower than CMOS, in ultra-low power regime). The overall decrease in the Power Delay Products (PDPs) are 88% and 77%, respectively, in the proposed CNFET and CGOT THA circuits compared to the CMOS THA.
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    Gate-Overlap Tunnel Field-Effect Transistors (GOTFETs) for Ultra-Low-Voltage and Ultra-Low-Power VLSI Applications
    (CRC, 2021) Vidhyadharan, Sanjay
    The advancement in complementary metal oxide semiconductor (CMOS) technology during the last few decades has enabled scaling down of the metal oxide semiconductor field-effect transistor (MOSFET) feature size to below the 100 nano meter (nm) range. The power supply voltage across the devices must be reduced proportionately with the reduction in feature size to maintain the electric fields inside the device within junction breakdown limits. The gate overlaps the source completely, while it is terminated 22 nm short of the channel-drain junction. The gate overlaps the source completely, while it is terminated 22 nm short of the channel-drain junction. Jitter is the variation of the clock edge from its ideal instance. Clock jitter is usually caused by the clock generating circuit, noise, power supply fluctuations, and interference from adjacent components.