A simple and direct technique for interface characterization of SOI MOSFETs and its application in hot carrier degradation studies in sub-100 nm JVD MNSFETs

Abstract

Conventional interface characterization techniques, such as charge pumping, cannot be applied to SOI devices due to lack of a substrate contact in these devices. A lock-in-amplifier based multi-frequency transconductance technique for interface characterization of sub-micron SOI MOSFETs has been implemented and used to study generation of interface states with stress. The technique has been validated on bulk MOSFETs using charge pumping measurements. Subsequently, it has been used to characterize hot carrier generated interface states in 100 nm SOI MNSFETs with silicon nitride gate dielectric deposited by the Jet-Vapor-Deposition process. Hot carrier stress studies on these MNSFETs show that the degradation is marginally lower in SOI MNSFETs as compared to identical bulk devices. This can be attributed to lower fields, and therefore impact generation, and absence of hot carriers caused by injection of carriers from the substrate.