Model for threshold voltage instability in top-gated nanocrystalline silicon thin film transistor

Abstract

The analytical model for the threshold voltage instability in top-gated staggered nanocrystalline silicon thin-film transistor is reported. This novel model includes the effect of various physical parameters like grain size, gate insulator thickness, doping density and grain boundary trapping state on the threshold voltage shift which is never reported earlier. It is observed that the higher trap density, greater doping concentration and larger gate insulator thickness provide lesser threshold voltage shift. Further, it is found from the results of grain size analysis that if grain size is smaller than threshold voltage shift decreases with decrease in grain size. However, if grain size is larger (Dg>20nm) then device become stable and shows negligible threshold voltage shift. In this paper, threshold voltage shift under gate bias voltage is also analyzed and result reveals that threshold voltage increases with the bias voltage. The calculated results are compared with experimental data. The close match between the two confirms the validity of proposed study.