100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectric

dc.contributor.authorRao, V. Ramgopal
dc.date.accessioned2023-11-07T10:19:17Z
dc.date.available2023-11-07T10:19:17Z
dc.date.issued1999
dc.description.abstractMetal-nitride-semiconductor (MNS) FETs with channel lengths down to 100 nm with a novel jet vapor deposited (JVD) SiN insulator as gate dielectric are fabricated and characterized for their electrical performance. By employing the charge pumping technique, the SiN interface quality and its effect on the transistor performance are evaluated. We show that, compared to conventional SiO/sub 2/ MOSFETs, the SiN devices show lower gate leakage current, competitive drain current drive and transconductance, good interface quality, and reduced hot-carrier degradation.en_US
dc.identifier.urihttps://ieeexplore.ieee.org/document/799349
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12900
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectSilicon compoundsen_US
dc.subjectMOSFETsen_US
dc.subjectTransconductanceen_US
dc.subjectHot carriersen_US
dc.subjectDegradationen_US
dc.title100 nm channel length MNSFETs using a jet vapor deposited ultra-thin silicon nitride gate dielectricen_US
dc.typeArticleen_US

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