Hardware Security of Scan Chain

Abstract

The scan test is majorly used for testing the integrated circuits since scan chain architecture provides very good controllability and observability. This advantage might give an attacker an opportunity to obtain sensitive information thus leading to security issues. The motivation of this paper is to focus on circuit security maintaining the test quality i.e., good controllability and observability. In this proposed paper a new scan chain design has been suggested which has relatively less security issues as compared to the existing methods. The only requirement to operate in the test mode for the suggested method is the correct test authorization password. The attacker would not be able to obtain the desired scan data without valid test authorization, thus preventing scan based attacks (SBA). Another method has also been proposed in which EXOR gates are used in the middle of scan flip-flops to give inverted input to the scan chain leading to a two-level security.