Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes

Abstract

Dynamic power dissipation depends on the switching activity of the circuit. In this paper we analyzed power consumption of TG based D flip-flop at different technology nodes and power saving obtained by applying dynamic XOR based clock gating technique to this flip-flop. This work deals with implementation of a transmission gate based D flip-flop in 3 different technology nodes namely 32 nm, 22 nm and 16 nm. The circuit level simulation result of D flip-flop shows power consumption with and without clock gating at the several frequencies of operation and several data activity factors at these technology nodes. Although the power dissipation decreases with the lower technology node, the additional power saving may be obtained using the dynamic XOR based clock gating approach at higher frequency of operation and low data activity, which has been investigated in this research work.