Integrated Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes

Abstract

Switching activities in a circuit results in the dynamic power dissipation of a circuit. In this work we investigated power consumption of transmission gate (TG) based D flip-flop designed using different technology nodes and power saving obtained by applying integrated clock gating (ICG) technique to this flip-flop. This work deals with implementation of a transmission gate-based D flip-flop in 3 different technology nodes, viz. 32 nm, 22 nm and 16 nm. The circuit level simulation was carried out using LTSPICE tool. The simulation result of D flip-flop shows power consumption with and without ICG at the different frequencies of operation and different data activity factors at these technology nodes. Although the power dissipation decreases with scaling down the technology node, the additional power saving may be obtained using the ICG approach at higher frequency of operation and high data activity factor, which has been investigated in this research work.