Design and Analysis of a Scan Chain in Subthreshold Region

Abstract

Testing of manufactured Integrated Circuit (IC) is performed using design for testability (DFT) techniques such as scan chain which is most popular in sequential circuits. The scan cell involves the modification of a D flip-flop (DFF) with a multiplexer at its input. During testing, a pattern is applied through the scan input pin (SI) in which individual flip-flops toggle their values as the test patterns are shifted in hence a significant amount of power is consumed in scan chain. Although moving to a lower technology node decreases the power consumption in a circuit, a further drastic reduction (i.e. 10 6 order) in power consumption is obtained by operating the circuit in the subthreshold region. In this work scan chain is designed to operate correctly in the subthreshold region using suitable device sizes, using both transmission gate (TG) based and true single phase clocked (TSPC) logic for 16, 22 & 32 nm technology nodes. Further, their average powers are compared. In addition, the Monte Carlo simulation and comparative analysis are performed to study the effect of variation of power supply and temperature.