Understanding the Impact of Process Variations on Analog Circuit Performance with Halo Channel Doped Deep Sub-Micron CMOS Technologies

Abstract

Single Halo (SH) and Double Halo (DH) MOSFETs are reported to suppress short channel effects in the sub 100nm regime [1]-[2]. Also, it has recently been shown that SH technologies exhibit good analog performance (higher output resistance and intrinsic MOSFET gain), even down to the sub 100 nm gate length regime [3]-[4]. However, the sensitivity of device and circuit performance parameters on the process variations still needs to be systematically investigated for all these technologies. In this work we present the effect of process variations on analog circuit performance parameters and the impact of halo doping on the circuit linearity with these technologies. Extensive 2-D process, device and mixed mode simulations have been performed to understand this aspect.