Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders
| dc.contributor.author | Gupta, Anu | |
| dc.contributor.author | Shekhar, Chandra | |
| dc.date.accessioned | 2023-02-10T04:06:03Z | |
| dc.date.available | 2023-02-10T04:06:03Z | |
| dc.date.issued | 2005-12 | |
| dc.description.abstract | The objective is to explore various adder architectures using different logic‐design styles and transistor‐sizes for different operand sizes. The scope of this work is the development of tools, which can be used to predict an optimum adder design for a given application based on the speed and energy‐consumption constraints | en_US |
| dc.identifier.uri | https://www.emerald.com/insight/content/doi/10.1108/13565360510610503/full/html | |
| dc.identifier.uri | http://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/9133 | |
| dc.language.iso | en | en_US |
| dc.publisher | Emerald | en_US |
| dc.subject | EEE | en_US |
| dc.subject | Architecture | en_US |
| dc.subject | Low power | en_US |
| dc.title | Performance exploration of adder architectures for small to moderate‐sized low‐power, high‐performance adders | en_US |
| dc.type | Article | en_US |
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