Design and ASIC implementation of column compression Wallace/Dadda multiplier in sub-threshold regime

Abstract

In this paper, the design and comparative analysis is done in between the most well-known column compression multipliers by Wallace [5] and Dadda [6] in sub-threshold regime. In order to reduce the hardware which ultimately reduces an area and power, energy efficient basic modules AND gates, half adders, full adders and partial product generate units have been analyzed. At the last stage ripple carry adder (RCA) and Han-Carlson adder are used to implement Wallace and Dadda multiplier. The performance metrics considered for the analysis of the adders are: power, delay and PDP. Simulation studies are carried out for 8x8 input data width. The proposed circuits show an energy efficient agreement with Spectre simulations using 45nm CMOS technology at 0.4V supply voltage. The proposed Wallace/Dadda multipliers using Han-Carlson adder (HCA) outperform its counterparts exhibiting low power consumption and lesser propagation delay as compared to Wallace/Dadda multipliers using RCA operated in the subthreshold region