Mitigating the Impact of Channel Tapering in Vertical Channel 3-D NAND

Abstract

The channel tapering from top to bottom in vertical channel 3-D NAND is a major concern. This leads to nonuniformity in the NAND string performance, including cell current (Icell) and threshold voltage (VT) variation along the vertical NAND string. In this article, we show that the variation in the electric field due to the difference in the channel radius from bottom to top is the root cause behind the VT variation along the string. For the first time, we propose novel techniques to minimize the adverse effects of the channel tapering on VT variations. It is shown that graded channel doping (~1018 cm-3 at the bottom to ~ 1015 cm-3 at the top) results in the narrowing of the VT variation by ~90% along the vertical string. Further, we propose that a nonuniform block oxide thickness along the string can be used to enhanced uniformity of VT distribution from bottom to top. Additionally, we investigate and show that the uniformity in VT distribution among word line (WL) transistors can also be achieved by optimizing the amplitude and duration of the position-dependent program/erase voltages. The proposed techniques in this article have a high potential for designing variation tolerant and reliable 3-D NAND memories having enhanced uniformity in the program/erase VT and Icell distribution.