A Comparison of Adiabatic Logic Circuit Techniques for an Energy Efficient 1-Bit Full Adder Design

Abstract

Power dissipation has become a critical design constraint in portable applications like a hand held computer due to limited battery life and reliability of integrated circuits. In this paper, a detailed comparison of five adiabatic logic families is carried out by simulation using SPICE. The simulation results are obtained for full adders, which are designed using the different design techniques with a view to design an energy efficient 1-bit full adder. The parameters compared are average energy consumption per addition, instantaneous peak power dissipation, number of transistors required, and operating frequency range. Average energy consumption per addition of full adders is found to vary with the variation in power-clock as well as input signal frequencies. An optimum value of power-clock frequency at which minimum energy consumption occurs at a fixed input signal frequency is obtained for all circuit techniques. Full adders circuits are designed using 0.5 μm CMOS technology.