Study of Degradation in Channel Initiated Secondary Electron Injection Regime

dc.contributor.authorRao, V. Ramgopal
dc.date.accessioned2023-11-07T07:07:56Z
dc.date.available2023-11-07T07:07:56Z
dc.date.issued2001-09
dc.description.abstractThis paper analyzes the Channel Initiated Secondary Electron injection mechanism and the resulting hot-carrier degradation in deep sub-micron n-channel MOSFETs. The correlation between gate (IG) and substrate current (IB) has been studied for different values of substrate bias. Stress and charge pumping measurements have been carried out to study the degradation under identical substrate bias and gate current conditions. Results show that under identical gate current (programming time for flash memory cells), the degradation is less for higher negative substrate bias.en_US
dc.identifier.urihttps://ieeexplore.ieee.org/document/1506640
dc.identifier.urihttp://dspace.bits-pilani.ac.in:8080/xmlui/handle/123456789/12891
dc.language.isoenen_US
dc.publisherIEEEen_US
dc.subjectEEEen_US
dc.subjectDegradationen_US
dc.subjectCurrent measurementen_US
dc.subjectNonvolatile memoryen_US
dc.subjectMOSFETsen_US
dc.subjectHot carriersen_US
dc.subjectCharge pumpingen_US
dc.titleStudy of Degradation in Channel Initiated Secondary Electron Injection Regimeen_US
dc.typeArticleen_US

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