A comparative analysis of power and delay optimise digital logic families for high performance system design

Abstract

In this paper, we propose a high performance system design methodology taking the best average delay on prime. Our analysis method is based on the commonly used logical effort methodology, extended to the least delay to find the transistors sizing. Simulation results are tabulated using SPECTRE in 0.18 µm CMOS technology as applied to three different logic styles including static CMOS, pseudo-NMOS and skewed logic. We observe that NAND based pseudo-NMOS logic design having NMOS width as 1 µm exhibits least delay but with enormous power dissipation, evaluated by the tool, whereas, skewed logic style response is better in terms of total power. Thus, the method used accurately shows the trade-off in power-delay of a given circuit, allowing a designer to choose the most appropriate logic style.