Off-State Leakage Concern in Scaling Nanowire FETs

Abstract

In this work, the simulation-based performance comparisons of the Si nanowire FET have been done for gate length scaling from 90 to 32 nm technology node. The study involves the design and optimization of the critical parameters for improved electrostatic control on the channel. The impact of gate length scaling on the off-state leakage current and threshold voltage roll-off concepts has been discussed. The study reports a drain current enhancement of 48.72 and 72.12% for gate length scaling from 90 to 45 nm and 90 nm to 32 nm technology node, respectively. The maximum mobility of the carrier up to 1173.86 cm−2/V. sand Ion/Ioff ratio of ~109 has been reported.