Design and Realization of High-Speed Low-Noise Multi-Loop Skew-Based ROs Optimized for Even/Odd Multi-Phase Signals

Abstract

This brief presents a general approach for generating high-frequency multiphase signals (even/odd), low phase noise, low power, and reduced supply sensitivity ring oscillators (ROs). For the same, multi-loop skew based single-ended ring oscillators (MSSROs) are designed and systematic analysis is performed. The topology is based on a unique feedback/feed-forward mechanism for realizing a fast loop in a long chain RO wherein the PMOS/NMOS of the stages are separately driven. This unique connection in MSSROs results in a skew offset (negative/positive/zero) which is generated between the inputs of PMOS/NMOS as the number of stages are increased. Therefore, MSSROs provide the time period equal to that of 3-stage single-ended conventional ROs (SCRO) and a better phase noise (7–11%) even with a larger number of stages (even/odd). A model is developed to predict the oscillation frequency and skew offset. The proposed methodology is validated in commercial 65nm and 180nm CMOS technologies, also indicating scalability of the proposed designs at scaled CMOS nodes. The simulations show that, depending on the number of stages, the operating frequency of the MSSROs varies from −25 (−11) % (positive-skew) to +16 (13) % (negative-skew) of its 3-stage SCRO counterparts in the 180nm (65nm) CMOS technology. Moreover, for a target phase noise and center frequency, the MSSROs consume about 8–30 (5–23) % lower power and up to 8% lower supply sensitivity as compared to its 3-stage SCRO counterparts in the 180nm (65nm) CMOS technology. The MSSRO also has a better PVT variation tolerance compared to SCRO.