A Novel Decoder Design for Logic Computation in SRAM: CiM-SRAM

Abstract

Computing-in-Memory is an emerging paradigm that promises to accelerate data-intensive computation by eliminating the back and forth data movement between the memory and processor. SRAM is an ideal candidate for implementing computation in memory as it offers benefits such as high speed, low power consumption, and high endurance. One of the most extensively explored techniques utilized to realize computation within the SRAM is reading out the voltage at the bitline, which corresponds to a valid logic function output. It also requires activation of multiple wordlines corresponding to the location of the stored operands in the memory. However, conventional address decoders in SRAM selects only one address at a time. Hence, addressing this challenge, we propose to design a novel decoder which support enabling of multiple wordline in a 6T bitcell based CiM-SRAM (Computing-in-Memory based SRAM) array for performing logic computation.